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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
| commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
| tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdk8/misc_control.c | |
| parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
| download | coreboot-5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9.tar.xz | |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdk8/misc_control.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 9b521eef79..a2b4651a4a 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -81,7 +81,7 @@ static void set_agp_aperture(device_t dev) /* Update the other northbridges */ pdev = 0; - while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { + while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { /* Store the GART size but don't enable it */ pci_write_config32(pdev, 0x90, gart_acr); @@ -160,7 +160,7 @@ static void misc_control_init(struct device *dev) needs_reset = 1; /* Needed? */ } } - else if(is_cpu_pre_d0()) { + else if (is_cpu_pre_d0()) { struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); @@ -174,7 +174,7 @@ static void misc_control_init(struct device *dev) cmd_ref = 0x000D0701; /* Unbuffered */ } cmd = pci_read_config32(dev, 0xd4); - if(cmd != cmd_ref) { + if (cmd != cmd_ref) { pci_write_config32(dev, 0xd4, cmd_ref ); needs_reset = 1; /* Needed? */ } @@ -185,7 +185,7 @@ static void misc_control_init(struct device *dev) if (f0_dev) { int link; cmd_ref = cmd = pci_read_config32(dev, 0xdc); - for(link = 0; link < 3; link++) { + for (link = 0; link < 3; link++) { uint32_t link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ |