- 1.1.4

  Major restructuring of hypertransport handling.
  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
  Updates to hard_reset handling when resetting because of the need to change hypertransport link
    speeds and widths.
    (a) No longer assume the boot is good just because we get to a hard reset point.
    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
       boot counter.
  Updates to arima/hdama mptable so it tracks the new bus numbers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 37 insertions, 0 deletions

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
new file mode 100644
index 0000000000..639e34fbaf
--- /dev/null
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -0,0 +1,37 @@
+/* Turn off machine check triggers when reading
+ * pci space where there are no devices.
+ * This is necessary when scaning the bus for
+ * devices which is done by the kernel */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+static void misc_control_init(struct device *dev)
+{
+	uint32_t cmd;
+	
+	printk_debug("NB: Function 3 Misc Control.. ");
+	cmd = pci_read_config32(dev, 0x44);
+	cmd |= (1<<6) | (1<<25);
+	pci_write_config32(dev, 0x44, cmd );
+
+	printk_debug("done.\n");
+}
+
+static struct device_operations mcf3_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = misc_control_init,
+	.scan_bus         = 0,
+};
+
+static struct pci_driver mcf3_driver __pci_driver = {
+	.ops    = &mcf3_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x1103,
+};
+