diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 22:06:29 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-14 22:06:29 +0000 |
| commit | 1944680bfd0a8ff6ec8df06d142ab143806e92f9 (patch) | |
| tree | 5e97a1fa5169b7a1d373cc069d20045146da59b3 /src/northbridge/amd/amdk8/misc_control.c | |
| parent | 5d7dafea868f9e0dfc47249c33e819ace04f78e5 (diff) | |
| download | coreboot-1944680bfd0a8ff6ec8df06d142ab143806e92f9.tar.xz | |
- Sync up northbridge/amd/amdk8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/misc_control.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 4938c453d7..e5e8f4c78f 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -42,7 +42,7 @@ static void mcf3_read_resources(device_t dev) pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) { + if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 3)) { return; } @@ -68,19 +68,20 @@ static void set_agp_aperture(device_t dev) if (resource) { device_t pdev; uint32_t gart_base, gart_acr; + /* Remember this resource has been stored */ resource->flags |= IORESOURCE_STORED; - /*Find the size of the GART aperture */ - gart_acr = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0); + /* Find the size of the GART aperture */ + gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; /* Update the other northbriges */ pdev = 0; - while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) { - /* Store GART size but don't enable it */ + while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { + /* Store the GART size but don't enable it */ pci_write_config32(pdev, 0x90, gart_acr); /* Store the GART base address */ @@ -175,8 +176,6 @@ static void misc_control_init(struct device *dev) needs_reset = 1; /* Needed? */ } } -#if CONFIG_MAX_CPUS > 1 -/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */ /* Optimize the Link read pointers */ f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3); if (f0_dev) { @@ -202,7 +201,6 @@ static void misc_control_init(struct device *dev) else { printk_err("Missing f0 device!\n"); } -#endif if (needs_reset) { printk_debug("resetting cpu\n"); hard_reset(); @@ -217,6 +215,7 @@ static struct device_operations mcf3_ops = { .enable_resources = pci_dev_enable_resources, .init = misc_control_init, .scan_bus = 0, + .ops_pci = 0, }; static struct pci_driver mcf3_driver __pci_driver = { |