diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
| commit | 83b991afff40e12a8b6756af06a472842edb1a66 (patch) | |
| tree | a441ff0d88afcb0a07cf22dc3653db3e07a05c98 /src/northbridge/amd/amdk8/misc_control.c | |
| parent | 080038bfbd8fdf08bac12476a3789495e6f705ca (diff) | |
| download | coreboot-83b991afff40e12a8b6756af06a472842edb1a66.tar.xz | |
- O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/misc_control.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 639e34fbaf..045f5cef06 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -8,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "./cpu_rev.c" static void misc_control_init(struct device *dev) { @@ -17,7 +18,48 @@ static void misc_control_init(struct device *dev) cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); + if (is_cpu_pre_c0()) { + /* errata 58 */ + cmd = pci_read_config32(dev, 0x80); + cmd &= ~(1<<0); + pci_write_config32(dev, 0x80, cmd ); + cmd = pci_read_config32(dev, 0x84); + cmd &= ~(1<<24); + cmd &= ~(1<<8); + pci_write_config32(dev, 0x84, cmd ); + /* errata 66 */ + cmd = pci_read_config32(dev, 0x70); + cmd &= ~(1<<0); + cmd |= (1<<1); + pci_write_config32(dev, 0x70, cmd ); + cmd = pci_read_config32(dev, 0x7c); + cmd &= ~(3<<4); + pci_write_config32(dev, 0x7c, cmd ); + } + else { + /* errata 98 */ +#if 0 + cmd = pci_read_config32(dev, 0xd4); + if(cmd != 0x04e20707) { + cmd = 0x04e20707; + pci_write_config32(dev, 0xd4, cmd ); + hard_reset(); + } +#endif + cmd = 0x04e20707; + pci_write_config32(dev, 0xd4, cmd ); + } +#if 1 + cmd = pci_read_config32(dev, 0xdc); + if((cmd & 0x0000ff00) != 0x02500) { + cmd &= 0xffff00ff; + cmd |= 0x00002500; + pci_write_config32(dev, 0xdc, cmd ); + printk_debug("resetting cpu\n"); + hard_reset(); + } +#endif printk_debug("done.\n"); } |