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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-27 19:37:31 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 04:40:27 +0200 |
| commit | 0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch) | |
| tree | b97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/amd/amdk8/raminit.c | |
| parent | 081651b6677c64a5f2861d831822b5f8f3517c21 (diff) | |
| download | coreboot-0f92f630556b4bf2e4c0696cae4c2f8e97eda334.tar.xz | |
Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index f3194503a9..19f83b998e 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -284,14 +284,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl) * 111 = reserved * [ 7: 7] Reserved * [12: 8] Tref (Refresh Rate) - * 00000 = 100Mhz 4K rows - * 00001 = 133Mhz 4K rows - * 00010 = 166Mhz 4K rows - * 00011 = 200Mhz 4K rows - * 01000 = 100Mhz 8K/16K rows - * 01001 = 133Mhz 8K/16K rows - * 01010 = 166Mhz 8K/16K rows - * 01011 = 200Mhz 8K/16K rows + * 00000 = 100MHz 4K rows + * 00001 = 133MHz 4K rows + * 00010 = 166MHz 4K rows + * 00011 = 200MHz 4K rows + * 01000 = 100MHz 8K/16K rows + * 01001 = 133MHz 8K/16K rows + * 01010 = 166MHz 8K/16K rows + * 01011 = 200MHz 8K/16K rows * [19:13] Reserved * [22:20] Twcl (Write CAS Latency) * 000 = 1 Mem clock after CAS# (Unbuffered Dimms) @@ -414,12 +414,12 @@ static void sdram_set_registers(const struct mem_controller *ctrl) * 0 = Use Idle Cycle Limit * 1 = Generate a dynamic Idle cycle limit * [22:20] DRAM MEMCLK Frequency - * 000 = 100Mhz + * 000 = 100MHz * 001 = reserved - * 010 = 133Mhz + * 010 = 133MHz * 011 = reserved * 100 = reserved - * 101 = 166Mhz + * 101 = 166MHz * 110 = reserved * 111 = reserved * [24:23] Reserved |