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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-06 21:50:21 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-06 21:50:21 +0000 |
| commit | 8f2c616dbc7f36bf63d61960c2e14c6ca1c5af22 (patch) | |
| tree | b1ede5972569c6aeb57961a5fdbd219019902c8f /src/northbridge/amd/amdk8/raminit_f.c | |
| parent | 233f186e95cf76d3a5bb5a7224769f63c36c5931 (diff) | |
| download | coreboot-8f2c616dbc7f36bf63d61960c2e14c6ca1c5af22.tar.xz | |
No warnings day, next round.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f.c')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index e34187154c..cac9f80097 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -707,12 +707,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in printk(BIOS_SPEW, "done.\n"); } +#if 0 static int is_dual_channel(const struct mem_controller *ctrl) { uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_Width128; } +#endif static int is_opteron(const struct mem_controller *ctrl) { @@ -727,6 +729,7 @@ static int is_opteron(const struct mem_controller *ctrl) return !!(nbcap & NBCAP_128Bit); } +#if 0 static int is_registered(const struct mem_controller *ctrl) { /* Test to see if we are dealing with registered SDRAM. @@ -737,7 +740,7 @@ static int is_registered(const struct mem_controller *ctrl) dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBuffDimm); } - +#endif static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { @@ -2481,6 +2484,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2491,6 +2495,7 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl) pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } +#endif /* DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20 |