diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdk8/raminit_f_dqs.c | |
parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
download | coreboot-5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9.tar.xz |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdk8/raminit_f_dqs.c')
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 262 |
1 files changed, 131 insertions, 131 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 0b777d18ac..567a8b6343 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -23,7 +23,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s%x\n", str, val); } #endif @@ -32,7 +32,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level static inline void print_debug_dqs_pair(const char *str, unsigned val, const char *str2, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); } #endif @@ -41,7 +41,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } #endif @@ -59,7 +59,7 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct int i; sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); - for(i=0;i<8; i++) { + for (i=0;i<8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); } @@ -87,10 +87,10 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i dword += mem_base; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 hole_reg = sysinfo->hole_reg[nodeid]; - if(hole_reg & 1) { + if (hole_reg & 1) { unsigned hole_startk; hole_startk = (hole_reg & (0xff<<24)) >> 10; - if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { dword += ((4*1024*1024 - hole_startk)<<2); } } @@ -196,7 +196,7 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; - if(p==1) { buf = buf_b; } + if (p==1) { buf = buf_b; } else { buf = buf_a; } set_FSBASE (addr>>24); @@ -241,8 +241,8 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned uint32_t value_test; unsigned result = DQS_FAIL; - if(Pass == DQS_FIRST_PASS) { - if(pattern==1) { + if (Pass == DQS_FIRST_PASS) { + if (pattern==1) { test_buf = (uint32_t *)TestPattern1; } else { @@ -257,7 +257,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned addr_lo = addr<<8; - if(is_Width128 && (channel == 1)) { + if (is_Width128 && (channel == 1)) { addr_lo += 8; //second channel test_buf += 2; } @@ -273,7 +273,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); - if(value == value_test) { + if (value == value_test) { addr_lo += 4; test_buf++; __asm__ volatile ( @@ -284,13 +284,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); - if(value == value_test){ + if (value == value_test){ result = DQS_PASS; } } - if(Pass == DQS_SECOND_PASS) { // second pass need to be inverted - if(result==DQS_PASS) { + if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted + if (result==DQS_PASS) { result = DQS_FAIL; } else { @@ -408,7 +408,7 @@ static uint16_t get_exact_T1000(unsigned i) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if( cpuid1.edx & 0x02 ) { + if ( cpuid1.edx & 0x02 ) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -424,7 +424,7 @@ static uint16_t get_exact_T1000(unsigned i) index = fid_start>>25; } - if(index>12) return T1000_a[i]; + if (index>12) return T1000_a[i]; return TT_a[index * 4+i]; @@ -436,14 +436,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) uint32_t dword; dword = 0x00000000; - for(i=1; i<=3; i++) { + for (i=1; i<=3; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); } dword = 0x2f2f2f2f; - for(i=5; i<=7; i++) { + for (i=5; i<=7; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); @@ -512,7 +512,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st unsigned cpu_f0_f1 = 0; #endif - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { InitDQSPos4RcvrEn(ctrl); } @@ -529,10 +529,10 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id); - if(!cpu_f0_f1) + if (!cpu_f0_f1) #endif { #if 1 @@ -553,14 +553,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? - if(Pass==DQS_FIRST_PASS) { - for(i=0;i<16;i++) { + if (Pass==DQS_FIRST_PASS) { + for (i=0;i<16;i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; } } else { - for(i=0;i<16;i++) { + for (i=0;i<16;i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; } @@ -586,21 +586,21 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st /* for each rank */ /* there are four receiver pairs, loosely associated with CS */ - for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); - if(is_Width128) { - if(channel) { + if (is_Width128) { + if (channel) { dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); CurrRcvrCHADelay= dword & 0xff; } } else { - if(channel) { + if (channel) { index += 0x20; } } @@ -608,7 +608,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st LastTest = DQS_FAIL; RcvrEnDlyRmin = 0xaf; - if(!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; + if (!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; /* for each DQS receiver enable setting */ @@ -616,7 +616,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st TestAddr0B = TestAddr0 + (1<<(20+2-8)); // 4MB - if(RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { + if (RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { TestAddr1 = Get_RcvrSysAddr(ctrl, channel, receiver+1, sysinfo); TestAddr1B = TestAddr1 + (1<<(20+2-8)); //4MB two_ranks = 1; @@ -630,12 +630,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st Write1LTestPattern(TestAddr0, 0, buf_a, buf_b); // rank0 of dimm, test p0 Write1LTestPattern(TestAddr0B, 1, buf_a, buf_b); //rank0 of dimm, test p1 - if(two_ranks == 1) { + if (two_ranks == 1) { Write1LTestPattern(TestAddr1, 0, buf_a, buf_b); //rank 1 of dimm Write1LTestPattern(TestAddr1B, 1, buf_a, buf_b);//rank 1 of dimm } - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { RcvrEnDly = 0; } else { RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; @@ -644,7 +644,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st while ( RcvrEnDly < 0xaf) { // Sweep Delay value here print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); - if(RcvrEnDly & 1) { + if (RcvrEnDly & 1) { /* Odd steps get another pattern such that even and odd steps alternate. The pointers to the patterns will be swapped @@ -663,7 +663,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); /* FIXME: 64bit MUX */ - if(is_Width128) { + if (is_Width128) { /* Program current Receiver enable delay channel b */ pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); } @@ -685,7 +685,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { Read1LTestPattern(TestAddr0B); Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); @@ -695,20 +695,20 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); - if(Test1 == DQS_PASS) { - if(two_ranks) { + if (Test1 == DQS_PASS) { + if (two_ranks) { Read1LTestPattern(TestAddr1); Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr1); ResetDCTWrPtr(ctrl); - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { Read1LTestPattern(TestAddr1B); Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr1B); ResetDCTWrPtr(ctrl); - if(Test1 == DQS_PASS) { + if (Test1 == DQS_PASS) { CurrTest = DQS_PASS; } } @@ -722,8 +722,8 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); - if(CurrTest == DQS_PASS) { - if(LastTest == DQS_FAIL) { + if (CurrTest == DQS_PASS) { + if (LastTest == DQS_FAIL) { RcvrEnDlyRmin = RcvrEnDly; break; } @@ -749,25 +749,25 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); - if(RcvrEnDlyRmin == 0xaf) { + if (RcvrEnDlyRmin == 0xaf) { //no passing window Errors |= SB_NORCVREN; } - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { // We need a better value for DQSPos training RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; } else { RcvrEnDly = RcvrEnDlyRmin; } - if(RcvrEnDly > 0xae) { + if (RcvrEnDly > 0xae) { //passing window too narrow, too far delayed Errors |= SB_SmallRCVR; RcvrEnDly = 0xae; } - if(Pass == DQS_SECOND_PASS) { //second pass must average vales + if (Pass == DQS_SECOND_PASS) { //second pass must average vales RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/; RcvrEnDly >>= 1; } @@ -777,18 +777,18 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st //Set final RcvrEnDly for this DIMM and Channel pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); - if(is_Width128) { + if (is_Width128) { pci_write_config32_index_wait(ctrl->f2, 0x98, index+0x20, RcvrEnDly); // channel B - if(channel) { + if (channel) { pci_write_config32_index_wait(ctrl->f2, 0x98, index, CurrRcvrCHADelay); - if(RcvrEnDly > CurrRcvrCHADelay) { + if (RcvrEnDly > CurrRcvrCHADelay) { dword = RcvrEnDly - CurrRcvrCHADelay; } else { dword = CurrRcvrCHADelay - RcvrEnDly; } dword *= 50; - if(dword > T1000) { + if (dword > T1000) { Errors |= SB_CHA2BRCVREN; } } @@ -796,7 +796,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); - if(RcvrEnDly > CTLRMaxDelay) { + if (RcvrEnDly > CTLRMaxDelay) { CTLRMaxDelay = RcvrEnDly; } @@ -817,9 +817,9 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st dword |= ecc_bit; pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 - if(!cpu_f0_f1) + if (!cpu_f0_f1) #endif { dword = pci_read_config32(ctrl->f2, DRAM_CTRL); @@ -858,7 +858,7 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); shift = bytelane; - while(shift>3) { + while (shift>3) { shift-=4; } shift <<= 3; // 8 bit @@ -878,13 +878,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe dword = 0; dqs_delay &= 0xff; - for(i=0;i<4;i++) { + for (i=0;i<4;i++) { dword |= dqs_delay<<(i*8); } index = 1 + channel * 0x20 + direction * 4; - for(i=0; i<2; i++) { + for (i=0; i<2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); } @@ -894,7 +894,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d) { unsigned size_d; size_d = max_d-min_d; - if(size_d & 1) { //need round up + if (size_d & 1) { //need round up min_d++; } return ( min_d + (size_d>>1)); @@ -968,7 +968,7 @@ static void ReadL9TestPattern(unsigned addr_lo) static void ReadDQSTestPattern(unsigned addr_lo, unsigned pattern) { - if(pattern == 0) { + if (pattern == 0) { ReadL9TestPattern(addr_lo); } else { @@ -1028,7 +1028,7 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) { - if(pattern == 0){ + if (pattern == 0){ FlushDQSTestPattern_L9(addr_lo); } else { @@ -1049,13 +1049,13 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign test_buf = (uint32_t *)buf_a; - if(pattern && channel) { + if (pattern && channel) { addr_lo += 8; //second channel test_buf+= 2; } bytelane = 0; - for(i=0;i<9*64/4;i++) { + for (i=0;i<9*64/4;i++) { __asm__ volatile ( "movl %%fs:(%1), %0\n\t" :"=b"(value): "a" (addr_lo) @@ -1065,8 +1065,8 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); - for(j=0;j<4*8;j+=8) { - if(((value>>j)&0xff) != ((value_test>>j)& 0xff)) { + for (j=0;j<4*8;j+=8) { + if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } @@ -1075,8 +1075,8 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign } print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); - if(bytelane == 0) { - if(pattern == 1) { //dual channel + if (bytelane == 0) { + if (pattern == 1) { //dual channel addr_lo += 8; //skip over other channel's data test_buf += 2; } @@ -1115,14 +1115,14 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); - for(DQSDelay=0; DQSDelay<48; DQSDelay++) { + for (DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) } - for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 + for (ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); //FIXME: process 64MUXedMode - if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue; + if (!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue; BanksPresent = 1; TestAddr = Get_MCTSysAddr(ctrl, ChipSel, sysinfo); @@ -1132,17 +1132,17 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, //set fs and use fs prefix to access the mem set_FSBASE(TestAddr>>24); - if(Direction == DQS_READDIR) { + if (Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read so write at first", 0, 4); WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } - for(DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); - if(MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes + if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - if(Direction == DQS_WRITEDIR) { + if (Direction == DQS_WRITEDIR) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } @@ -1157,25 +1157,25 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, } } - if(BanksPresent) - for(ByteLane = 0; ByteLane < 8; ByteLane++) { + if (BanksPresent) + for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); LastTest = DQS_FAIL; RnkDlySeqPassMax = 0; RnkDlyFilterMax = 0; RnkDlyFilterMin = 0; - for(DQSDelay=0; DQSDelay<48; DQSDelay++) { - if(MutualCSPassW[DQSDelay] & (1<<ByteLane)) { + for (DQSDelay=0; DQSDelay<48; DQSDelay++) { + if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); RnkDlySeqPassMax = DQSDelay; - if(LastTest == DQS_FAIL) { + if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -1187,13 +1187,13 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, } print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); - if(RnkDlySeqPassMax == 0) { + if (RnkDlySeqPassMax == 0) { Errors |= SB_NODQSPOS; // no passing window } else { print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); - if((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ + if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ Errors |= SB_SMALLDQS; } else { @@ -1370,15 +1370,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in //SetupDqsPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); - if(is_Width128){ + if (is_Width128){ pattern = 1; - for(i=0;i<16*18;i++) { + for (i=0;i<16*18;i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; - for(i=0; i<16*9;i++) { + for (i=0; i<16*9;i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; } @@ -1396,27 +1396,27 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in channel = 1; } - while( (channel<2) && (!Errors)) { + while ( (channel<2) && (!Errors)) { print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); - for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { + for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay); print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); - if(err == 0) break; + if (err == 0) break; Errors |= err; } print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); - if(DQSWrDelay < 48) { + if (DQSWrDelay < 48) { Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); } channel++; - if(!is_Width128){ + if (!is_Width128){ //FIXME: 64MuxMode?? channel++; // skip channel if 64-bit mode } @@ -1457,7 +1457,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); - if(DQSDelay0>DQSDelay1) { + if (DQSDelay0>DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; InterFactor = 0xff - InterFactor; } @@ -1469,7 +1469,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay >>= 8; // /255 - if(DQSDelay0>DQSDelay1) { + if (DQSDelay0>DQSDelay1) { DQSDelay += DQSDelay1; } else { @@ -1494,8 +1494,8 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info ByteLane = 8; - for(channel = 0; channel < 2; channel++) { - for(i=0;i<2;i++) { + for (channel = 0; channel < 2; channel++) { + for (i=0;i<2;i++) { Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); @@ -1509,7 +1509,7 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); - if(TrainRcvrEn(ctrl, Pass, sysinfo)) { + if (TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); @@ -1519,7 +1519,7 @@ static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); - if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { + if (TrainDQSRdWrPos(ctrl, sysinfo) != 0) { printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id); return 1; } @@ -1540,18 +1540,18 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_addr("dqs_timing: tsc1[8] :", tsc1); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; uint32_t dword; cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); - if(!cpu_f0_f1[i]) continue; + if (!cpu_f0_f1[i]) continue; dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); dword &= ~DC_DqsRcvEnTrain; @@ -1567,7 +1567,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); dword = tsc1[i].lo + tsc0[i].lo; - if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { tsc1[i].hi++; } tsc1[i].lo = dword; @@ -1577,14 +1577,14 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl } - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - if(!cpu_f0_f1[i]) continue; + if (!cpu_f0_f1[i]) continue; tsc_t tsc; @@ -1672,7 +1672,7 @@ static unsigned int range_to_mtrr(unsigned int reg, if (!range_sizek || (reg >= 8)) { return reg; } - while(range_sizek) { + while (range_sizek) { unsigned long max_align, align; unsigned long sizek; /* Compute the maximum size I can make a range */ @@ -1735,7 +1735,7 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); //[4G, TOM2) - if(tom2_k) { + if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB @@ -1761,12 +1761,12 @@ static void clear_mtrr_dqs(unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - for(i=0x204;i<0x210;i++) { + for (i=0x204;i<0x210;i++) { wrmsr(i, msr); } //[4G, TOM2) - if(tom2_k) { + if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB @@ -1794,8 +1794,8 @@ static unsigned get_htic_bit(unsigned i, unsigned bit) static void wait_till_sysinfo_in_ram(void) { - while(1) { - if(get_htic_bit(0, 9)) return; + while (1) { + if (get_htic_bit(0, 9)) return; } } #endif @@ -1909,26 +1909,26 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } tsc[0] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); - if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; + if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); } @@ -1938,28 +1938,28 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc #endif tsc[2] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); - if(train_DqsPos(ctrl+i, sysinfo)) goto out; + if (train_DqsPos(ctrl+i, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); } tsc[3] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); - if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; + if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; #if CONFIG_HAVE_ACPI_RESUME @@ -1972,7 +1972,7 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); - for(i=0;i<5;i++) { + for (i=0;i<5;i++) { print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); } @@ -1992,7 +1992,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info tsc_t tsc[4]; - if(sysinfo->mem_trained[i] != 0x80) return; + if (sysinfo->mem_trained[i] != 0x80) return; #if CONFIG_MEM_TRAIN_SEQ == 1 //need to enable mtrr, so dqs training could access the test address @@ -2001,39 +2001,39 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info fill_mem_cs_sysinfo(i, ctrl, sysinfo); - if(v) { + if (v) { tsc[0] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i); } - if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { + if (train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[1] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } - if(train_DqsPos(ctrl, sysinfo)) { + if (train_DqsPos(ctrl, sysinfo)) { sysinfo->mem_trained[i]=0x82; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[2] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ + if (train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[3] = rdtsc(); @@ -2044,13 +2044,13 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); #endif - if(v) { - for(ii=0;ii<4;ii++) { + if (v) { + for (ii=0;ii<4;ii++) { print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } - if(sysinfo->mem_trained[i] == 0x80) { + if (sysinfo->mem_trained[i] == 0x80) { sysinfo->mem_trained[i]=1; } @@ -2069,7 +2069,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { - if(coreid) return; // only do it on core0 + if (coreid) return; // only do it on core0 struct sys_info *sysinfox; uintptr_t migrated_base = CONFIG_RAMTOP - car_data_size(); @@ -2077,7 +2077,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy wait_till_sysinfo_in_ram(); // use pci to get it - if(sysinfox->mem_trained[nodeid] == 0x80) { + if (sysinfox->mem_trained[nodeid] == 0x80) { #if 0 sysinfo->tom_k = sysinfox->tom_k; sysinfo->tom2_k = sysinfox->tom2_k; |