diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdk8 | |
parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
download | coreboot-5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9.tar.xz |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdk8')
-rw-r--r-- | src/northbridge/amd/amdk8/acpi.c | 34 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 140 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/debug.c | 42 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/early_ht.c | 12 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/f.h | 18 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/get_sblk_pci1234.c | 20 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/incoherent_ht.c | 58 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 8 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 78 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 4 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 6 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 262 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/raminit_test.c | 6 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/reset_test.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/setup_resource_map.c | 8 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/util.asl | 2 |
16 files changed, 350 insertions, 350 deletions
diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index db521dafc0..992a85ed46 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 l device_t cpu; int cpu_index = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { + for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; @@ -55,7 +55,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current) device_t cpu; int cpu_index = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { + for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; @@ -99,9 +99,9 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) * next range is from 1M--- * So will cut off before 1M in the mem range */ - if((basek+sizek)<1024) return; + if ((basek+sizek)<1024) return; - if(basek<1024) { + if (basek<1024) { sizek -= 1024 - basek; basek = 1024; } @@ -158,30 +158,30 @@ static unsigned long acpi_fill_slit(unsigned long current) p += 8; #if 0 - for(i=0;i<sysconf.hc_possible_num;i++) { - if((sysconf.pci1234[i]&1) !=1 ) continue; + for (i=0;i<sysconf.hc_possible_num;i++) { + if ((sysconf.pci1234[i]&1) !=1 ) continue; outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node } #endif - for(i=0;i<nodes;i++) { - for(j=0;j<nodes; j++) { - if(i==j) { + for (i=0;i<nodes;i++) { + for (j=0;j<nodes; j++) { + if (i==j) { p[i*nodes+j] = 10; } else { #if 0 int k; u8 latency_factor = 0; int k_start, k_end; - if(i<j) { + if (i<j) { k_start = i; k_end = j; } else { k_start = j; k_end = i; } - for(k=k_start;k<=k_end; k++) { - if(outer_node[k]) { + for (k=k_start;k<=k_end; k++) { + if (outer_node[k]) { latency_factor = 1; break; } @@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCLK"); acpigen_write_package(HC_POSSIBLE_NUM); - for(i=0;i<sysconf.hc_possible_num;i++) { + for (i=0;i<sysconf.hc_possible_num;i++) { acpigen_write_dword(sysconf.pci1234[i]); } - for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x0); } @@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) { acpigen_write_name("HCDN"); acpigen_write_package(HC_POSSIBLE_NUM); - for(i=0;i<sysconf.hc_possible_num;i++) { + for (i=0;i<sysconf.hc_possible_num;i++) { acpigen_write_dword(sysconf.hcdn[i]); } - for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 + for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 acpigen_write_dword(0x20202020); } acpigen_pop_len(); @@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_write_name(name); acpigen_write_package(dlen); - for(i=0; i<dlen; i++) { + for (i=0; i<dlen; i++) { dword = pci_read_config32(dev, offset+i*4); acpigen_write_dword(dword); } diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a7c3fc27c6..7dfc5ef13d 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -259,7 +259,7 @@ static int verify_connection(u8 dest) * remode node's vendor/device id */ val = pci_read_config32(NODE_HT(dest),0); - if(val != 0x11001022) + if (val != 0x11001022) return 0; return 1; @@ -368,18 +368,18 @@ static int optimize_connection(device_t node1, uint8_t link1, device_t node2, ui static uint8_t get_linkn_first(uint8_t byte) { - if(byte & 0x02) { byte = 0; } - else if(byte & 0x04) { byte = 1; } - else if(byte & 0x08) { byte = 2; } + if (byte & 0x02) { byte = 0; } + else if (byte & 0x04) { byte = 1; } + else if (byte & 0x08) { byte = 2; } return byte; } #if TRY_HIGH_FIRST == 1 static uint8_t get_linkn_last(uint8_t byte) { - if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } - if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } - if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } + if (byte & 0x02) { byte &= 0x0f; byte |= 0x00; } + if (byte & 0x04) { byte &= 0x0f; byte |= 0x10; } + if (byte & 0x08) { byte &= 0x0f; byte |= 0x20; } return byte>>4; } #endif @@ -388,9 +388,9 @@ static uint8_t get_linkn_last(uint8_t byte) static uint8_t get_linkn_last_count(uint8_t byte) { byte &= 0x0f; - if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } - if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } - if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } + if (byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } + if (byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } + if (byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } return byte>>4; } #endif @@ -400,7 +400,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo uint8_t linkn; uint32_t val; val = 1; - for(linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn<3; linkn++) { uint8_t regpos; uint32_t reg; regpos = 0x98 + 0x20 * linkn; @@ -420,7 +420,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) val = 1<<(linkn+1); val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/ - if(((source &1)!=(dest &1)) + if (((source &1)!=(dest &1)) #if CROSS_BAR_47_56 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here //(6,5) (7,4) should be here @@ -452,7 +452,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num) { int i; - for(i=0; i<num; i+=3) { + for (i=0; i<num; i+=3) { opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); } } @@ -469,7 +469,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num) { int i; - for(i=0; i<num; i+=3) { + for (i=0; i<num; i+=3) { opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); } } @@ -507,7 +507,7 @@ static void setup_remote_node(u8 node) printk(BIOS_SPEW, "setup_remote_node: "); /* copy the default resource map from node 0 */ - for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { + for (i = 0; i < ARRAY_SIZE(pci_reg); i++) { uint32_t value; uint8_t reg; reg = pci_reg[i]; @@ -534,7 +534,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif #if !CROSS_BAR_47_56 u8 gateway; u8 diff; - if(source<dest) { + if (source<dest) { gateway = source + 2; } else { gateway = source - 2; @@ -551,7 +551,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif diff = ((source&1)!=(dest &1)); #endif - if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ + if (diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ val_s -= val & 0xff; #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED uint8_t byte; @@ -560,13 +560,13 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif */ byte = val_s; byte = get_linkn_last_count(byte); - if((byte>>2)>1) { /* make sure not the corner*/ - if(source<dest) { + if ((byte>>2)>1) { /* make sure not the corner*/ + if (source<dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { #if CROSS_BAR_47_56 #if 0 - if(source==7) { + if (source==7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 } else if (source==6){ val_s-=link_connection(temp, 7); // for 6,3 via 4 @@ -584,7 +584,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif val |= (val_s<<8); } - if(diff) { /* cross rung?*/ + if (diff) { /* cross rung?*/ val |= (1<<16); } else { @@ -613,10 +613,10 @@ static void setup_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for(i=0; i<num; i+=2) { + for (i=0; i<num; i+=2) { setup_row_indirect(conn[i], conn[i+1]); #else - for(i=0; i<num; i+=4) { + for (i=0; i<num; i+=4) { setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif @@ -640,10 +640,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) int i; #if !CROSS_BAR_47_56 - for(i=0; i<num; i+=2) { + for (i=0; i<num; i+=2) { setup_remote_row_indirect(conn[i], conn[i+1]); #else - for(i=0; i<num; i+=4) { + for (i=0; i<num; i+=4) { setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]); #endif } @@ -667,7 +667,7 @@ static int optimize_connection_group(const u8 *opt_conn, int num) { int needs_reset = 0; int i; - for(i=0; i<num; i+=2) { + for (i=0; i<num; i+=2) { needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); @@ -688,7 +688,7 @@ static unsigned setup_smp2(void) val = get_row(0,0); byte = (val>>16) & 0xfe; - if(byte<0x2) { /* no coherent connection so get out.*/ + if (byte<0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } @@ -716,7 +716,7 @@ static unsigned setup_smp2(void) val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); - if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/ + if ((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/ val = get_row(0,0); byte = (val>>16) & 0xfe; #if TRY_HIGH_FIRST == 1 @@ -766,7 +766,7 @@ static unsigned setup_smp4(void) byte = ((val>>16) & 0xfe) - link_connection(0,1); byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have two coherent for 4p and above*/ + if ((byte>>2)==0) { /* We should have two coherent for 4p and above*/ nodes = 2; return nodes; } @@ -840,9 +840,9 @@ static unsigned setup_smp4(void) #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED /* We need to find out which link is to node3 */ - if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ + if ((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ val = get_row(7,3); - if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/ + if ((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/ val = get_row(2,2); byte = ((val>>16) & 0xfe) - link_connection(2,0); byte = get_linkn_first(byte); @@ -864,7 +864,7 @@ static unsigned setup_smp4(void) val = get_row(7,3); byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(3,5) link=", byte); setup_remote_row_direct(3, 5, byte); @@ -874,7 +874,7 @@ static unsigned setup_smp4(void) byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(2,4) link=", byte); setup_row_direct(2, 4, byte); @@ -937,7 +937,7 @@ static unsigned setup_smp6(void) byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + if ((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ nodes = 4; return nodes; } @@ -947,7 +947,7 @@ static unsigned setup_smp6(void) val = get_row(3,3); byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + if ((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ nodes = 4; return nodes; } @@ -974,7 +974,7 @@ static unsigned setup_smp6(void) setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1002,7 +1002,7 @@ static unsigned setup_smp6(void) enable_routing(4); setup_temp_row(0,1); - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte+1,byte+3); } verify_connection(7); @@ -1030,9 +1030,9 @@ static unsigned setup_smp6(void) #if CONFIG_MAX_PHYSICAL_CPUS > 6 /* We need to find out which link is to node5 */ - if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ + if ((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ val = get_row(7,5); - if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ + if ((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ val = get_row(4,4); byte = ((val>>16) & 0xfe) - link_connection(4,2); byte = get_linkn_first(byte); @@ -1053,7 +1053,7 @@ static unsigned setup_smp6(void) val = get_row(7,5); byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ byte &= 3; /*bit [3,2] is count-2*/ print_linkn("(5,7) link=", byte); setup_remote_row_direct(5, 7, byte); @@ -1064,7 +1064,7 @@ static unsigned setup_smp6(void) byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + if ((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ byte &= 3; /* bit [3,2] is count-2*/ print_linkn("(4,6) link=", byte); setup_row_direct(4, 6, byte); @@ -1114,7 +1114,7 @@ static unsigned setup_smp6(void) /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) * It will be done by clear_dead_links */ - for(byte=0; byte<4; byte++) { + for (byte=0; byte<4; byte++) { clear_temp_row(byte); } #endif @@ -1142,7 +1142,7 @@ static unsigned setup_smp8(void) #else byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); byte = get_linkn_last_count(byte); /* Max link to 6*/ - if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + if ((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; return nodes; } @@ -1150,7 +1150,7 @@ static unsigned setup_smp8(void) #if CROSS_BAR_47_56 byte = get_linkn_last_count(byte); /* Max link to 6*/ - if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/ + if ((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; return nodes; } @@ -1169,7 +1169,7 @@ static unsigned setup_smp8(void) val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + if ((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ nodes = 6; return nodes; } @@ -1202,7 +1202,7 @@ static unsigned setup_smp8(void) setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); - for(byte=0; byte<6; byte+=2) { + for (byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); @@ -1240,7 +1240,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte+1,byte+3); } setup_temp_row(5,6); @@ -1248,7 +1248,7 @@ static unsigned setup_smp8(void) verify_connection(7); val = get_row(7,6); // to chect it if it is node6 before renaming - if( (val>>16) == 1) { // it is real node 7 so swap it + if ( (val>>16) == 1) { // it is real node 7 so swap it /* We need to recompute link to 6 */ val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,3); @@ -1261,7 +1261,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 6, byte); #if 0 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte+1,byte+3); } #endif @@ -1281,7 +1281,7 @@ static unsigned setup_smp8(void) #if !CROSS_BAR_47_56 setup_temp_row(0,1); - for(byte=0; byte<6; byte+=2) { + for (byte=0; byte<6; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1301,7 +1301,7 @@ static unsigned setup_smp8(void) setup_row_direct(4, 7, byte); /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); } @@ -1326,7 +1326,7 @@ static unsigned setup_smp8(void) setup_row_direct(5, 7, byte); setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { + for (byte=0; byte<4; byte+=2) { setup_temp_row(byte+1,byte+3); } @@ -1485,17 +1485,17 @@ static unsigned setup_smp(void) nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes == 2) + if (nodes == 2) nodes = setup_smp4(); #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 - if(nodes == 4) + if (nodes == 4) nodes = setup_smp6(); #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes == 6) + if (nodes == 6) nodes = setup_smp8(); #endif @@ -1517,14 +1517,14 @@ static unsigned verify_mp_capabilities(unsigned nodes) switch(mask) { #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ - if(nodes > 2) { + if (nodes > 2) { printk(BIOS_ERR, "Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ - if(nodes >1 ) { + if (nodes >1 ) { printk(BIOS_ERR, "Going back to UP\n"); return 1; } @@ -1541,22 +1541,22 @@ static void clear_dead_routes(unsigned nodes) int last_row; int node, row; #if CONFIG_MAX_PHYSICAL_CPUS == 8 - if(nodes==8) return;/* don't touch (7,7)*/ + if (nodes==8) return;/* don't touch (7,7)*/ #endif last_row = nodes; if (nodes == 1) { last_row = 0; } - for(node = 7; node >= 0; node--) { - for(row = 7; row >= last_row; row--) { + for (node = 7; node >= 0; node--) { + for (row = 7; row >= last_row; row--) { fill_row(node, row, DEFAULT); } } /* Update the local row */ - for( node=0; node<nodes; node++) { + for ( node=0; node<nodes; node++) { uint32_t val = 0; - for(row =0; row<nodes; row++) { + for (row =0; row<nodes; row++) { val |= get_row(node, row); } fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); @@ -1651,7 +1651,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) { unsigned node; int needs_reset = 0; - for(node = 0; node < nodes; node++) { + for (node = 0; node < nodes; node++) { device_t dev; uint32_t cmd; dev = NODE_MC(node); @@ -1692,7 +1692,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) */ cmd_ref = 0x04e20707; /* Registered */ cmd = pci_read_config32(dev, 0xd4); - if(cmd != cmd_ref) { + if (cmd != cmd_ref) { pci_write_config32(dev, 0xd4, cmd_ref ); needs_reset = 1; /* Needed? */ } @@ -1721,14 +1721,14 @@ static int optimize_link_read_pointers(unsigned nodes) { unsigned node; int needs_reset = 0; - for(node = 0; node < nodes; node++) { + for (node = 0; node < nodes; node++) { device_t f0_dev, f3_dev; uint32_t cmd_ref, cmd; int link; f0_dev = NODE_HT(node); f3_dev = NODE_MC(node); cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc); - for(link = 0; link < 3; link++) { + for (link = 0; link < 3; link++) { uint32_t link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ @@ -1764,14 +1764,14 @@ static int optimize_link_coherent_ht(void) nodes = get_nodes(); #if CONFIG_MAX_PHYSICAL_CPUS > 1 - if(nodes>1) { + if (nodes>1) { needs_reset |= optimize_connection( NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); } #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes>2) { + if (nodes>2) { /* optimize physical connections - by LYH */ static const u8 opt_conn4[] = { 0,2, @@ -1783,7 +1783,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 - if(nodes>4) { + if (nodes>4) { static const uint8_t opt_conn6[] ={ 2, 4, 3, 5, @@ -1796,7 +1796,7 @@ static int optimize_link_coherent_ht(void) #endif #if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes>6) { + if (nodes>6) { static const uint8_t opt_conn8[] ={ 4, 6, #if CROSS_BAR_47_56 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index c1021e5736..35353bd64a 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -19,7 +19,7 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); + for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; @@ -31,10 +31,10 @@ static inline void print_pci_devices(void) } print_debug_pci_dev(dev); printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); - if(((dev>>12) & 0x07) == 0) { + if (((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if((hdr_type & 0x80) != 0x80) { + if ((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); } } @@ -46,7 +46,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); - for(i = 0; i < 256; i++) { + for (i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "\n%02x:",i); @@ -65,12 +65,12 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) print_debug_pci_dev(dev); printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg); - for(i = 0; i < 0x40; i++) { + for (i = 0; i < 0x40; i++) { uint32_t val; int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); - for(j=0;j<4;j++) { + for (j=0;j<4;j++) { printk(BIOS_DEBUG, " %02x", val & 0xff); val >>= 8; } @@ -83,7 +83,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); + for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; @@ -95,10 +95,10 @@ static inline void dump_pci_devices(void) } dump_pci_device(dev); - if(((dev>>12) & 0x07) == 0) { + if (((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if((hdr_type & 0x80) != 0x80) { + if ((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); } } @@ -108,7 +108,7 @@ static inline void dump_pci_devices(void) static inline void dump_pci_devices_on_bus(unsigned busn) { device_t dev; - for(dev = PCI_DEV(busn, 0, 0); + for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; @@ -120,10 +120,10 @@ static inline void dump_pci_devices_on_bus(unsigned busn) } dump_pci_device(dev); - if(((dev>>12) & 0x07) == 0) { + if (((dev>>12) & 0x07) == 0) { uint8_t hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); - if((hdr_type & 0x80) != 0x80) { + if ((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); } } @@ -136,13 +136,13 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; printk(BIOS_DEBUG, "\n"); - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; if (device) { int j; printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); - for(j = 0; j < 128; j++) { + for (j = 0; j < 128; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) { @@ -161,7 +161,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) if (device) { int j; printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); - for(j = 0; j < 128; j++) { + for (j = 0; j < 128; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) { @@ -182,11 +182,11 @@ static void dump_smbus_registers(void) { unsigned device; printk(BIOS_DEBUG, "\n"); - for(device = 1; device < 0x80; device++) { + for (device = 1; device < 0x80; device++) { int j; - if( smbus_read_byte(device, 0) < 0 ) continue; + if ( smbus_read_byte(device, 0) < 0 ) continue; printk(BIOS_DEBUG, "smbus: %02x", device); - for(j = 0; j < 256; j++) { + for (j = 0; j < 256; j++) { int status; unsigned char byte; status = smbus_read_byte(device, j); @@ -210,7 +210,7 @@ static inline void dump_io_resources(unsigned port) int i; udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); - for(i=0;i<256;i++) { + for (i=0;i<256;i++) { uint8_t val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); @@ -228,8 +228,8 @@ static inline void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); - for(i=start;i<end;i++) { - if((i & 0xf)==0) { + for (i=start;i<end;i++) { + if ((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 1bc34e42f1..8f6766d29a 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -47,7 +47,7 @@ static void enumerate_ht_chain(void) { pos = pci_read_config8(dev, PCI_CAPABILITY_LIST); } - while(pos != 0) { + while (pos != 0) { uint8_t cap; cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { @@ -64,8 +64,8 @@ static void enumerate_ht_chain(void) device_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. - if(!end_used) { + if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. + if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { @@ -114,20 +114,20 @@ static void enumerate_ht_chain(void) break; } } - } while((ctrl & (1 << 5)) == 0); + } while ((ctrl & (1 << 5)) == 0); break; } } pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); } - } while(last_unitid != next_unitid); + } while (last_unitid != next_unitid); out: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { + if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index f83282bfeb..a449c3412e 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -535,25 +535,25 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one CPU installed + if (sysinfo->nodes == 1) return; // in case only one CPU installed - for(i=1; i<sysinfo->nodes; i++) { + for (i=1; i<sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->mem_trained[i]==0x00) continue; + if (sysinfo->mem_trained[i]==0x00) continue; mask |= (1<<i); } i = 1; - while(1) { - if(mask & (1<<i)) { - if((sysinfo->mem_trained[i])!=0x80) { + while (1) { + if (mask & (1<<i)) { + if ((sysinfo->mem_trained[i])!=0x80) { mask &= ~(1<<i); } } - if(!mask) break; + if (!mask) break; #if 0 /* cpu_relax */ @@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) i%=sysinfo->nodes; } - for(i=0; i<sysinfo->nodes; i++) { + for (i=0; i<sysinfo->nodes; i++) { printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); switch(sysinfo->mem_trained[i]) { case 0: //don't need train @@ -577,7 +577,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) break; } } - if(needs_reset) { + if (needs_reset) { printk(BIOS_DEBUG, "mem trained failed\n"); #ifdef __PRE_RAM__ soft_reset(); diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 3818dd11dd..9cf40830e4 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -38,7 +38,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) if (!dev) { return 0; } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + for (reg = 0xE0; reg < 0xF0; reg += 0x04) { uint32_t config_map; unsigned dst_node; unsigned dst_link; @@ -211,22 +211,22 @@ void get_sblk_pci1234(void) dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for(j=0;j<4;j++) { + for (j=0;j<4;j++) { uint32_t dwordx; dwordx = pci_read_config32(dev, 0xe0 + j*4); dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ - if((dwordx & 0xff1) == dword) { /* SBLINK */ + if ((dwordx & 0xff1) == dword) { /* SBLINK */ sysconf.pci1234[0] = dwordx; sysconf.hcdn[0] = sysconf.hcdn_reg[j]; continue; } - if((dwordx & 1) == 1) { + if ((dwordx & 1) == 1) { /* We need to find out the number of HC * for exact match */ - for(i=1;i<sysconf.hc_possible_num;i++) { - if((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { + for (i=1;i<sysconf.hc_possible_num;i++) { + if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; break; @@ -234,8 +234,8 @@ void get_sblk_pci1234(void) } /* For 0xff0 match or same node */ - for(i=1;i<sysconf.hc_possible_num;i++) { - if((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { + for (i=1;i<sysconf.hc_possible_num;i++) { + if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) { sysconf.pci1234[i] = dwordx; sysconf.hcdn[i] = sysconf.hcdn_reg[j]; break; @@ -244,8 +244,8 @@ void get_sblk_pci1234(void) } } - for(i=1;i<sysconf.hc_possible_num;i++) { - if((sysconf.pci1234[i] & 1) != 1) { + for (i=1;i<sysconf.hc_possible_num;i++) { + if ((sysconf.pci1234[i] & 1) != 1) { sysconf.pci1234[i] = 0; sysconf.hcdn[i] = 0x20202020; } diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 12b8290dd1..de2a4b3bb1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -34,7 +34,7 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) if (pos > PCI_CAP_LIST_NEXT) { pos = pci_read_config8(dev, pos); } - while(pos != 0) { /* loop through the linked list */ + while (pos != 0) { /* loop through the linked list */ uint8_t cap; cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { @@ -69,13 +69,13 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid //actually, only for one HT device HT chain, and unitid is 0 #if !CONFIG_HT_CHAIN_UNITID_BASE - if(offset_unitid) { + if (offset_unitid) { return; } #endif /* Check if is already collapsed */ - if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { + if ((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { uint32_t id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -88,7 +88,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid /* Spin through the devices and collapse any previous * hypertransport enumeration. */ - for(dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) { + for (dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) { uint32_t id; uint8_t pos; uint16_t flags; @@ -167,7 +167,7 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) /* netlogic micro cap doesn't support 16 bit yet */ if (id == (0x184e | (0x0001 << 16))) { - if((width_cap & 0x77) == 0x11) { + if ((width_cap & 0x77) == 0x11) { width_cap &= 0x88; } } @@ -346,7 +346,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of break; } } - } while((ctrl & (1 << 5)) == 0); + } while ((ctrl & (1 << 5)) == 0); device_t dev = PCI_DEV(bus, 0, 0); last_unitid = next_unitid; @@ -371,9 +371,9 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid) { - if(next_unitid>= (bus ? 0x20:0x18) ) { - if(!end_used) { + if (offset_unitid) { + if (next_unitid>= (bus ? 0x20:0x18) ) { + if (!end_used) { next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { @@ -436,7 +436,7 @@ out: end_of_chain: ; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { + if (offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { uint16_t flags; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; @@ -446,14 +446,14 @@ end_of_chain: ; #if CONFIG_RAMINIT_SYSINFO // Here need to change the dev in the array int i; - for(i=0;i<sysinfo->link_pair_num;i++) + for (i=0;i<sysinfo->link_pair_num;i++) { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; - if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { + if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); continue; } - if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { + if (link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); } } @@ -605,13 +605,13 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned devn; reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); - if((reg & 3) != 3) continue; // not enabled + if ((reg & 3) != 3) continue; // not enabled nodeid = ((reg & 0xf0)>>4); // nodeid linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn - for(devn = 0; devn < 0x20; devn++) { + for (devn = 0; devn < 0x20; devn++) { reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1? if ( (reg & 0xffff) == vendorid ) { reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); @@ -731,7 +731,7 @@ static int ht_setup_chains_x(void) #endif /* clean others */ - for(ht_c_num=1;ht_c_num<4; ht_c_num++) { + for (ht_c_num=1;ht_c_num<4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); #if CONFIG_K8_ALLOCATE_IO_RANGE @@ -741,11 +741,11 @@ static int ht_setup_chains_x(void) #endif } - for(nodeid=0; nodeid<nodes; nodeid++) { + for (nodeid=0; nodeid<nodes; nodeid++) { device_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); - for(linkn = 0; linkn<3; linkn++) { + for (linkn = 0; linkn<3; linkn++) { unsigned regpos; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(dev, regpos); @@ -753,15 +753,15 @@ static int ht_setup_chains_x(void) print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); tempreg = 3 | (nodeid <<4) | (linkn<<8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ - for(ht_c_num=0;ht_c_num<4; ht_c_num++) { + for (ht_c_num=0;ht_c_num<4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); - if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ + if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ break; } } - if(ht_c_num == 4) break; /*used up only 4 non conherent allowed*/ + if (ht_c_num == 4) break; /*used up only 4 non conherent allowed*/ /*update to 0xe0...*/ - if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */ + if ((reg & 0xf) == 3) continue; /*SbLink so don't touch it */ print_linkn_in("\tbusn=", next_busn); tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); @@ -780,11 +780,11 @@ static int ht_setup_chains_x(void) } /*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/ - for(nodeid = 1; nodeid<nodes; nodeid++) { + for (nodeid = 1; nodeid<nodes; nodeid++) { int i; device_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); - for(i = 0; i< 4; i++) { + for (i = 0; i< 4; i++) { unsigned regpos; regpos = 0xe0 + i * 4; reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); @@ -793,13 +793,13 @@ static int ht_setup_chains_x(void) #if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ - for(i = 0; i< 4; i++) { + for (i = 0; i< 4; i++) { unsigned regpos; regpos = 0xc4 + i * 8; reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); pci_write_config32(dev, regpos, reg); } - for(i = 0; i< 4; i++) { + for (i = 0; i< 4; i++) { unsigned regpos; regpos = 0xc0 + i * 8; reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos); @@ -810,9 +810,9 @@ static int ht_setup_chains_x(void) /* recount ht_c_num*/ uint8_t i=0; - for(ht_c_num=0;ht_c_num<4; ht_c_num++) { + for (ht_c_num=0;ht_c_num<4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); - if(((reg & 0xf) != 0x0)) { + if (((reg & 0xf) != 0x0)) { i++; } } @@ -838,7 +838,7 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo) printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); - for(i=0; i< link_pair_num; i++) { + for (i=0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 9b521eef79..a2b4651a4a 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -81,7 +81,7 @@ static void set_agp_aperture(device_t dev) /* Update the other northbridges */ pdev = 0; - while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { + while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { /* Store the GART size but don't enable it */ pci_write_config32(pdev, 0x90, gart_acr); @@ -160,7 +160,7 @@ static void misc_control_init(struct device *dev) needs_reset = 1; /* Needed? */ } } - else if(is_cpu_pre_d0()) { + else if (is_cpu_pre_d0()) { struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); @@ -174,7 +174,7 @@ static void misc_control_init(struct device *dev) cmd_ref = 0x000D0701; /* Unbuffered */ } cmd = pci_read_config32(dev, 0xd4); - if(cmd != cmd_ref) { + if (cmd != cmd_ref) { pci_write_config32(dev, 0xd4, cmd_ref ); needs_reset = 1; /* Needed? */ } @@ -185,7 +185,7 @@ static void misc_control_init(struct device *dev) if (f0_dev) { int link; cmd_ref = cmd = pci_read_config32(dev, 0xdc); - for(link = 0; link < 3; link++) { + for (link = 0; link < 3; link++) { uint32_t link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c4fd3fdcee..d80c565d78 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -47,7 +47,7 @@ static unsigned fx_devs=0; static void get_fx_devs(void) { int i; - for(i = 0; i < MAX_FX_DEVS; i++) { + for (i = 0; i < MAX_FX_DEVS; i++) { __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1)); if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) @@ -70,7 +70,7 @@ static void f1_write_config32(unsigned reg, u32 value) int i; if (fx_devs == 0) get_fx_devs(); - for(i = 0; i < fx_devs; i++) { + for (i = 0; i < fx_devs; i++) { device_t dev; dev = __f1_dev[i]; if (dev && dev->enabled) { @@ -144,7 +144,7 @@ static void amdk8_scan_chain(struct bus *link) * register in function 1. */ free_reg = 0; - for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { + for (config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { u32 config; config = f1_read_config32(config_reg); if (!free_reg && ((config & 3) == 0)) { @@ -265,12 +265,12 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, unsigned nodeid, link = 0; int result; res = 0; - for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { device_t dev; dev = __f0_dev[nodeid]; if (!dev) continue; - for(link = 0; !res && (link < 3); link++) { + for (link = 0; !res && (link < 3); link++) { res = probe_resource(dev, IOINDEX(0x100 + reg, link)); } } @@ -293,7 +293,7 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, unsigned free_reg, reg; resource = 0; free_reg = 0; - for(reg = min; reg <= max; reg += 0x8) { + for (reg = min; reg <= max; reg += 0x8) { int result; result = reg_useable(reg, dev, nodeid, link); if (result == 1) { @@ -370,7 +370,7 @@ static void amdk8_read_resources(device_t dev) unsigned nodeid; struct bus *link; nodeid = amdk8_nodeid(dev); - for(link = dev->link_list; link; link = link->next) { + for (link = dev->link_list; link; link = link->next) { if (link->children) { amdk8_link_read_bases(dev, nodeid, link->link_num); } @@ -489,7 +489,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= link->secondary ) && + if ((vga_pri->bus->secondary >= link->secondary ) && (vga_pri->bus->secondary <= link->subordinate ) ) #endif @@ -505,7 +505,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) /* allocate a temp resource for the legacy VGA buffer */ resource = new_resource(dev, IOINDEX(4, link->link_num)); - if(!resource){ + if (!resource){ printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev)); return; } @@ -526,7 +526,7 @@ static void amdk8_set_resources(device_t dev) nodeid = amdk8_nodeid(dev); /* Set each resource we have found */ - for(res = dev->resource_list; res; res = res->next) { + for (res = dev->resource_list; res; res = res->next) { struct resource *old = NULL; unsigned index; @@ -554,7 +554,7 @@ static void amdk8_set_resources(device_t dev) compact_resources(dev); - for(bus = dev->link_list; bus; bus = bus->next) { + for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -609,7 +609,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Find the already assigned resource pairs */ get_fx_devs(); - for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { u32 base, limit; base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); @@ -685,7 +685,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } hole = pci_read_config32(__f1_dev[i], 0xf0); - if(hole & 1) { // we find the hole + if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole @@ -695,9 +695,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) /* We need to double check if there is special set on base reg and limit reg * are not continuous instead of hole, it will find out its hole_startk. */ - if(mem_hole.node_id==-1) { + if (mem_hole.node_id==-1) { u32 limitk_pri = 0; - for(i=0; i<8; i++) { + for (i=0; i<8; i++) { u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); @@ -706,7 +706,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } base_k = (base & 0xffff0000) >> 2; - if(limitk_pri != base_k) { // we find the hole + if (limitk_pri != base_k) { // we find the hole mem_hole.hole_startk = limitk_pri; mem_hole.node_id = i; break; //only one hole @@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) hole_sizek = (4*1024*1024) - hole_startk; - for(i=7;i>node_id;i--) { + for (i=7;i>node_id;i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -756,7 +756,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) return; } hoist = pci_read_config32(dev, 0xf0); - if(hoist & 1) { + if (hoist & 1) { pci_write_config32(dev, 0xf0, 0); } else { base = pci_read_config32(dev, 0x40 + (node_id << 3)); @@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) carry_over = (4*1024*1024) - hole_startk; - for(i=7;i>node_id;i--) { + for (i=7;i>node_id;i--) { base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -790,7 +790,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) dev = __f1_dev[node_id]; base = pci_read_config32(dev, 0x40 + (node_id << 3)); basek = (base & 0xffff0000) >> 2; - if(basek == hole_startk) { + if (basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow //so need to change base reg instead, new basek will be 4*1024*1024 base &= 0x0000ffff; @@ -904,8 +904,8 @@ static void amdk8_domain_set_resources(device_t dev) //mmio_basek = 3*1024*1024; // for debug to meet boundary - if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + if (reset_memhole) { + if (mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); @@ -923,7 +923,7 @@ static void amdk8_domain_set_resources(device_t dev) } basek = (base & 0xffff0000) >> 2; - if(mmio_basek == basek) { + if (mmio_basek == basek) { mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node break; } @@ -939,7 +939,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif idx = 0x10; - for(i = 0; i < fx_devs; i++) { + for (i = 0; i < fx_devs; i++) { u32 base, limit; u32 basek, limitk, sizek; base = f1_read_config32(0x40 + (i << 3)); @@ -974,7 +974,7 @@ static void amdk8_domain_set_resources(device_t dev) if (basek <= mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - if(pre_sizek>0) { + if (pre_sizek>0) { ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; @@ -982,9 +982,9 @@ static void amdk8_domain_set_resources(device_t dev) ramtop = mmio_basek * 1024; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - if(reset_memhole) + if (reset_memhole) #if !CONFIG_K8_REV_F_SUPPORT - if(!is_cpu_pre_e0() ) + if (!is_cpu_pre_e0() ) #endif sizek += hoist_memory(mmio_basek,i); #endif @@ -1025,7 +1025,7 @@ static void amdk8_domain_scan_bus(device_t dev) struct bus *link = dev->link_list; /* Unmap all of the HT chains */ - for(reg = 0xe0; reg <= 0xec; reg += 4) { + for (reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } @@ -1037,7 +1037,7 @@ static void amdk8_domain_scan_bus(device_t dev) * Including enabling relaxed ordering if it is safe. */ get_fx_devs(); - for(i = 0; i < fx_devs; i++) { + for (i = 0; i < fx_devs; i++) { device_t f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { @@ -1158,7 +1158,7 @@ static void cpu_bus_scan(device_t dev) if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; - if(bsp_apicid == 0) { + if (bsp_apicid == 0) { /* bsp apic id is not changed */ sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else @@ -1174,7 +1174,7 @@ static void cpu_bus_scan(device_t dev) /* Always use the devicetree node with lapic_id 0 for BSP. */ remap_bsp_lapic(cpu_bus); - for(i = 0; i < sysconf.nodes; i++) { + for (i = 0; i < sysconf.nodes; i++) { device_t cpu_dev; /* Find the cpu's pci device */ @@ -1185,7 +1185,7 @@ static void cpu_bus_scan(device_t dev) */ int local_j; device_t dev_f0; - for(local_j = 0; local_j <= 3; local_j++) { + for (local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); } @@ -1193,7 +1193,7 @@ static void cpu_bus_scan(device_t dev) * otherwise the device under it will not be scanned */ dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); - if(dev_f0) { + if (dev_f0) { add_more_links(dev_f0, 3); } } @@ -1205,12 +1205,12 @@ static void cpu_bus_scan(device_t dev) j = (j >> 12) & 3; // dev is func 3 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cpu_dev), j); - if(nb_cfg_54) { + if (nb_cfg_54) { // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... // ----> you can mixed single core e0 and dual core e0 at any sequence // That is the typical case - if(j == 0 ){ + if (j == 0 ){ #if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else @@ -1219,13 +1219,13 @@ static void cpu_bus_scan(device_t dev) } else { e0_later_single_core = 0; } - if(e0_later_single_core) { + if (e0_later_single_core) { printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); j=1; } - if(siblings > j ) { + if (siblings > j ) { } else { siblings = j; @@ -1236,7 +1236,7 @@ static void cpu_bus_scan(device_t dev) } u32 jj; - if(e0_later_single_core || disable_siblings) { + if (e0_later_single_core || disable_siblings) { jj = 0; } else { @@ -1245,7 +1245,7 @@ static void cpu_bus_scan(device_t dev) for (j = 0; j <=jj; j++ ) { u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - if(sysconf.enabled_apic_ext_id) { + if (sysconf.enabled_apic_ext_id) { if (apic_id != 0 || sysconf.lift_bsp_apicid) { apic_id += sysconf.apicid_offset; } diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index f502287d22..a9516d8d28 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2445,7 +2445,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) if ((loops & 1023) == 0) { printk(BIOS_DEBUG, "."); } - } while(((dcl & whatWait) != 0) && (loops < TIMEOUT_LOOPS)); + } while (((dcl & whatWait) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { printk(BIOS_DEBUG, " failed\n"); continue; @@ -2460,7 +2460,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) #endif do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); - } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) || + } while (((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) || ((dcl & DCL_SRS))); } diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 8ed0335703..765fea1f15 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1647,7 +1647,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if( cpuid1.edx & 0x02 ) { + if ( cpuid1.edx & 0x02 ) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -3118,7 +3118,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, if ((loops & 1023) == 0) { printk(BIOS_DEBUG, "."); } - } while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); + } while (((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { printk(BIOS_DEBUG, " failed\n"); continue; @@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* Wait until it is safe to touch memory */ do { dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); - } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); + } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 if (cpu_f0_f1[i]) { diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 0b777d18ac..567a8b6343 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -23,7 +23,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s%x\n", str, val); } #endif @@ -32,7 +32,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level static inline void print_debug_dqs_pair(const char *str, unsigned val, const char *str2, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); } #endif @@ -41,7 +41,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val, unsigned val2, unsigned level) { #if DQS_TRAIN_DEBUG > 0 - if(DQS_TRAIN_DEBUG > level) { + if (DQS_TRAIN_DEBUG > level) { printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } #endif @@ -59,7 +59,7 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct int i; sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3)); - for(i=0;i<8; i++) { + for (i=0;i<8; i++) { sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2)); } @@ -87,10 +87,10 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i dword += mem_base; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 hole_reg = sysinfo->hole_reg[nodeid]; - if(hole_reg & 1) { + if (hole_reg & 1) { unsigned hole_startk; hole_startk = (hole_reg & (0xff<<24)) >> 10; - if( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { + if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) { dword += ((4*1024*1024 - hole_startk)<<2); } } @@ -196,7 +196,7 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) { uint8_t *buf; - if(p==1) { buf = buf_b; } + if (p==1) { buf = buf_b; } else { buf = buf_a; } set_FSBASE (addr>>24); @@ -241,8 +241,8 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned uint32_t value_test; unsigned result = DQS_FAIL; - if(Pass == DQS_FIRST_PASS) { - if(pattern==1) { + if (Pass == DQS_FIRST_PASS) { + if (pattern==1) { test_buf = (uint32_t *)TestPattern1; } else { @@ -257,7 +257,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned addr_lo = addr<<8; - if(is_Width128 && (channel == 1)) { + if (is_Width128 && (channel == 1)) { addr_lo += 8; //second channel test_buf += 2; } @@ -273,7 +273,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.lo : addr_lo = ", addr_lo, " value = ", value, 4); - if(value == value_test) { + if (value == value_test) { addr_lo += 4; test_buf++; __asm__ volatile ( @@ -284,13 +284,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4); print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4); - if(value == value_test){ + if (value == value_test){ result = DQS_PASS; } } - if(Pass == DQS_SECOND_PASS) { // second pass need to be inverted - if(result==DQS_PASS) { + if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted + if (result==DQS_PASS) { result = DQS_FAIL; } else { @@ -408,7 +408,7 @@ static uint16_t get_exact_T1000(unsigned i) /* Check for FID control support */ struct cpuid_result cpuid1; cpuid1 = cpuid(0x80000007); - if( cpuid1.edx & 0x02 ) { + if ( cpuid1.edx & 0x02 ) { /* Use current FID */ unsigned fid_cur; msr = rdmsr(0xc0010042); @@ -424,7 +424,7 @@ static uint16_t get_exact_T1000(unsigned i) index = fid_start>>25; } - if(index>12) return T1000_a[i]; + if (index>12) return T1000_a[i]; return TT_a[index * 4+i]; @@ -436,14 +436,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) uint32_t dword; dword = 0x00000000; - for(i=1; i<=3; i++) { + for (i=1; i<=3; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); } dword = 0x2f2f2f2f; - for(i=5; i<=7; i++) { + for (i=5; i<=7; i++) { /* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */ pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword); pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword); @@ -512,7 +512,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st unsigned cpu_f0_f1 = 0; #endif - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { InitDQSPos4RcvrEn(ctrl); } @@ -529,10 +529,10 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 cpu_f0_f1 = is_cpu_pre_f2_in_bsp(ctrl->node_id); - if(!cpu_f0_f1) + if (!cpu_f0_f1) #endif { #if 1 @@ -553,14 +553,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st // SetupRcvrPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? - if(Pass==DQS_FIRST_PASS) { - for(i=0;i<16;i++) { + if (Pass==DQS_FIRST_PASS) { + for (i=0;i<16;i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; } } else { - for(i=0;i<16;i++) { + for (i=0;i<16;i++) { *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; } @@ -586,21 +586,21 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st /* for each rank */ /* there are four receiver pairs, loosely associated with CS */ - for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) + for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { unsigned index=(receiver>>1) * 3 + 0x10; print_debug_dqs("\t\tTrainRcvEn52: index ", index, 2); - if(is_Width128) { - if(channel) { + if (is_Width128) { + if (channel) { dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); CurrRcvrCHADelay= dword & 0xff; } } else { - if(channel) { + if (channel) { index += 0x20; } } @@ -608,7 +608,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st LastTest = DQS_FAIL; RcvrEnDlyRmin = 0xaf; - if(!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; + if (!RcvrRankEnabled(ctrl, channel, receiver, is_Width128, sysinfo)) continue; /* for each DQS receiver enable setting */ @@ -616,7 +616,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st TestAddr0B = TestAddr0 + (1<<(20+2-8)); // 4MB - if(RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { + if (RcvrRankEnabled(ctrl, channel, receiver+1, is_Width128, sysinfo)) { TestAddr1 = Get_RcvrSysAddr(ctrl, channel, receiver+1, sysinfo); TestAddr1B = TestAddr1 + (1<<(20+2-8)); //4MB two_ranks = 1; @@ -630,12 +630,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st Write1LTestPattern(TestAddr0, 0, buf_a, buf_b); // rank0 of dimm, test p0 Write1LTestPattern(TestAddr0B, 1, buf_a, buf_b); //rank0 of dimm, test p1 - if(two_ranks == 1) { + if (two_ranks == 1) { Write1LTestPattern(TestAddr1, 0, buf_a, buf_b); //rank 1 of dimm Write1LTestPattern(TestAddr1B, 1, buf_a, buf_b);//rank 1 of dimm } - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { RcvrEnDly = 0; } else { RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver]; @@ -644,7 +644,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st while ( RcvrEnDly < 0xaf) { // Sweep Delay value here print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); - if(RcvrEnDly & 1) { + if (RcvrEnDly & 1) { /* Odd steps get another pattern such that even and odd steps alternate. The pointers to the patterns will be swapped @@ -663,7 +663,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); /* FIXME: 64bit MUX */ - if(is_Width128) { + if (is_Width128) { /* Program current Receiver enable delay channel b */ pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); } @@ -685,7 +685,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn542: Test0 ", Test0, 3); - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { Read1LTestPattern(TestAddr0B); Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); @@ -695,20 +695,20 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn543: Test1 ", Test1, 3); - if(Test1 == DQS_PASS) { - if(two_ranks) { + if (Test1 == DQS_PASS) { + if (two_ranks) { Read1LTestPattern(TestAddr1); Test0 = CompareTestPatternQW0(channel, TestAddr1, PatternA, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr1); ResetDCTWrPtr(ctrl); - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { Read1LTestPattern(TestAddr1B); Test1 = CompareTestPatternQW0(channel, TestAddr1B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr1B); ResetDCTWrPtr(ctrl); - if(Test1 == DQS_PASS) { + if (Test1 == DQS_PASS) { CurrTest = DQS_PASS; } } @@ -722,8 +722,8 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\t\tTrainRcvEn55: RcvrEnDly ", RcvrEnDly, 3); - if(CurrTest == DQS_PASS) { - if(LastTest == DQS_FAIL) { + if (CurrTest == DQS_PASS) { + if (LastTest == DQS_FAIL) { RcvrEnDlyRmin = RcvrEnDly; break; } @@ -749,25 +749,25 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); - if(RcvrEnDlyRmin == 0xaf) { + if (RcvrEnDlyRmin == 0xaf) { //no passing window Errors |= SB_NORCVREN; } - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { // We need a better value for DQSPos training RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; } else { RcvrEnDly = RcvrEnDlyRmin; } - if(RcvrEnDly > 0xae) { + if (RcvrEnDly > 0xae) { //passing window too narrow, too far delayed Errors |= SB_SmallRCVR; RcvrEnDly = 0xae; } - if(Pass == DQS_SECOND_PASS) { //second pass must average vales + if (Pass == DQS_SECOND_PASS) { //second pass must average vales RcvrEnDly += dqs_rcvr_dly_a[channel * 8 + receiver] /* - (RCVREN_MARGIN * T1000/64/50)*/; RcvrEnDly >>= 1; } @@ -777,18 +777,18 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st //Set final RcvrEnDly for this DIMM and Channel pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly); - if(is_Width128) { + if (is_Width128) { pci_write_config32_index_wait(ctrl->f2, 0x98, index+0x20, RcvrEnDly); // channel B - if(channel) { + if (channel) { pci_write_config32_index_wait(ctrl->f2, 0x98, index, CurrRcvrCHADelay); - if(RcvrEnDly > CurrRcvrCHADelay) { + if (RcvrEnDly > CurrRcvrCHADelay) { dword = RcvrEnDly - CurrRcvrCHADelay; } else { dword = CurrRcvrCHADelay - RcvrEnDly; } dword *= 50; - if(dword > T1000) { + if (dword > T1000) { Errors |= SB_CHA2BRCVREN; } } @@ -796,7 +796,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\t\tTrainRcvEn63: RcvrEnDly ", RcvrEnDly, 2); - if(RcvrEnDly > CTLRMaxDelay) { + if (RcvrEnDly > CTLRMaxDelay) { CTLRMaxDelay = RcvrEnDly; } @@ -817,9 +817,9 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st dword |= ecc_bit; pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword); - if(Pass == DQS_FIRST_PASS) { + if (Pass == DQS_FIRST_PASS) { #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 - if(!cpu_f0_f1) + if (!cpu_f0_f1) #endif { dword = pci_read_config32(ctrl->f2, DRAM_CTRL); @@ -858,7 +858,7 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2); shift = bytelane; - while(shift>3) { + while (shift>3) { shift-=4; } shift <<= 3; // 8 bit @@ -878,13 +878,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe dword = 0; dqs_delay &= 0xff; - for(i=0;i<4;i++) { + for (i=0;i<4;i++) { dword |= dqs_delay<<(i*8); } index = 1 + channel * 0x20 + direction * 4; - for(i=0; i<2; i++) { + for (i=0; i<2; i++) { pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword); } @@ -894,7 +894,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d) { unsigned size_d; size_d = max_d-min_d; - if(size_d & 1) { //need round up + if (size_d & 1) { //need round up min_d++; } return ( min_d + (size_d>>1)); @@ -968,7 +968,7 @@ static void ReadL9TestPattern(unsigned addr_lo) static void ReadDQSTestPattern(unsigned addr_lo, unsigned pattern) { - if(pattern == 0) { + if (pattern == 0) { ReadL9TestPattern(addr_lo); } else { @@ -1028,7 +1028,7 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo) static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) { - if(pattern == 0){ + if (pattern == 0){ FlushDQSTestPattern_L9(addr_lo); } else { @@ -1049,13 +1049,13 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign test_buf = (uint32_t *)buf_a; - if(pattern && channel) { + if (pattern && channel) { addr_lo += 8; //second channel test_buf+= 2; } bytelane = 0; - for(i=0;i<9*64/4;i++) { + for (i=0;i<9*64/4;i++) { __asm__ volatile ( "movl %%fs:(%1), %0\n\t" :"=b"(value): "a" (addr_lo) @@ -1065,8 +1065,8 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7); - for(j=0;j<4*8;j+=8) { - if(((value>>j)&0xff) != ((value_test>>j)& 0xff)) { + for (j=0;j<4*8;j+=8) { + if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) { bitmap &= ~(1<<bytelane); } @@ -1075,8 +1075,8 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign } print_debug_dqs("\t\t\t\t\t\tbitmap = ", bitmap, 7); - if(bytelane == 0) { - if(pattern == 1) { //dual channel + if (bytelane == 0) { + if (pattern == 1) { //dual channel addr_lo += 8; //skip over other channel's data test_buf += 2; } @@ -1115,14 +1115,14 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW); - for(DQSDelay=0; DQSDelay<48; DQSDelay++) { + for (DQSDelay=0; DQSDelay<48; DQSDelay++) { MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS) } - for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 + for (ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7 print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); //FIXME: process 64MUXedMode - if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue; + if (!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue; BanksPresent = 1; TestAddr = Get_MCTSysAddr(ctrl, ChipSel, sysinfo); @@ -1132,17 +1132,17 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, //set fs and use fs prefix to access the mem set_FSBASE(TestAddr>>24); - if(Direction == DQS_READDIR) { + if (Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read so write at first", 0, 4); WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } - for(DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ + for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5); - if(MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes + if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); - if(Direction == DQS_WRITEDIR) { + if (Direction == DQS_WRITEDIR) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a); } @@ -1157,25 +1157,25 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, } } - if(BanksPresent) - for(ByteLane = 0; ByteLane < 8; ByteLane++) { + if (BanksPresent) + for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); LastTest = DQS_FAIL; RnkDlySeqPassMax = 0; RnkDlyFilterMax = 0; RnkDlyFilterMin = 0; - for(DQSDelay=0; DQSDelay<48; DQSDelay++) { - if(MutualCSPassW[DQSDelay] & (1<<ByteLane)) { + for (DQSDelay=0; DQSDelay<48; DQSDelay++) { + if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5); print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); RnkDlySeqPassMax = DQSDelay; - if(LastTest == DQS_FAIL) { + if (LastTest == DQS_FAIL) { RnkDlySeqPassMin = DQSDelay; //start sequential run } - if((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ + if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){ RnkDlyFilterMin = RnkDlySeqPassMin; RnkDlyFilterMax = RnkDlySeqPassMax; } @@ -1187,13 +1187,13 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, } print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); - if(RnkDlySeqPassMax == 0) { + if (RnkDlySeqPassMax == 0) { Errors |= SB_NODQSPOS; // no passing window } else { print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4); print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4); - if((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ + if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){ Errors |= SB_SMALLDQS; } else { @@ -1370,15 +1370,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in //SetupDqsPattern buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); - if(is_Width128){ + if (is_Width128){ pattern = 1; - for(i=0;i<16*18;i++) { + for (i=0;i<16*18;i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; - for(i=0; i<16*9;i++) { + for (i=0; i<16*9;i++) { *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; } @@ -1396,27 +1396,27 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in channel = 1; } - while( (channel<2) && (!Errors)) { + while ( (channel<2) && (!Errors)) { print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1); - for(DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { + for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) { unsigned err; SetDQSDelayAllCSR(ctrl, channel, DQS_WRITEDIR, DQSWrDelay); print_debug_dqs("\t\tTrainDQSRdWrPos: 21 DQSWrDelay ", DQSWrDelay, 2); err= TrainReadDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); print_debug_dqs("\t\tTrainDQSRdWrPos: 22 err ",err, 2); - if(err == 0) break; + if (err == 0) break; Errors |= err; } print_debug_dqs("\tTrainDQSRdWrPos: 3 DQSWrDelay ", DQSWrDelay, 1); - if(DQSWrDelay < 48) { + if (DQSWrDelay < 48) { Errors = TrainWriteDQS(ctrl, channel, pattern, buf_a, dqs_delay_a, sysinfo); print_debug_dqs("\tTrainDQSRdWrPos: 4 Errors ", Errors, 1); } channel++; - if(!is_Width128){ + if (!is_Width128){ //FIXME: 64MuxMode?? channel++; // skip channel if 64-bit mode } @@ -1457,7 +1457,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a); DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a); - if(DQSDelay0>DQSDelay1) { + if (DQSDelay0>DQSDelay1) { DQSDelay = DQSDelay0 - DQSDelay1; InterFactor = 0xff - InterFactor; } @@ -1469,7 +1469,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte DQSDelay >>= 8; // /255 - if(DQSDelay0>DQSDelay1) { + if (DQSDelay0>DQSDelay1) { DQSDelay += DQSDelay1; } else { @@ -1494,8 +1494,8 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info ByteLane = 8; - for(channel = 0; channel < 2; channel++) { - for(i=0;i<2;i++) { + for (channel = 0; channel < 2; channel++) { + for (i=0;i<2;i++) { Direction = direction[i]; lane0 = 4; lane1 = 5; ratio = 0; dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a); @@ -1509,7 +1509,7 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); - if(TrainRcvrEn(ctrl, Pass, sysinfo)) { + if (TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); @@ -1519,7 +1519,7 @@ static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); - if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { + if (TrainDQSRdWrPos(ctrl, sysinfo) != 0) { printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id); return 1; } @@ -1540,18 +1540,18 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_addr("dqs_timing: tsc1[8] :", tsc1); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; uint32_t dword; cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); - if(!cpu_f0_f1[i]) continue; + if (!cpu_f0_f1[i]) continue; dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL); dword &= ~DC_DqsRcvEnTrain; @@ -1567,7 +1567,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2); dword = tsc1[i].lo + tsc0[i].lo; - if((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { + if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) { tsc1[i].hi++; } tsc1[i].lo = dword; @@ -1577,14 +1577,14 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl } - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; - if(!cpu_f0_f1[i]) continue; + if (!cpu_f0_f1[i]) continue; tsc_t tsc; @@ -1672,7 +1672,7 @@ static unsigned int range_to_mtrr(unsigned int reg, if (!range_sizek || (reg >= 8)) { return reg; } - while(range_sizek) { + while (range_sizek) { unsigned long max_align, align; unsigned long sizek; /* Compute the maximum size I can make a range */ @@ -1735,7 +1735,7 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k) range_to_mtrr(2, 0, tom_k,4*1024*1024, MTRR_TYPE_WRBACK, 40); //[4G, TOM2) - if(tom2_k) { + if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB @@ -1761,12 +1761,12 @@ static void clear_mtrr_dqs(unsigned tom2_k) wrmsr(0x258, msr); //[1M, TOM) - for(i=0x204;i<0x210;i++) { + for (i=0x204;i<0x210;i++) { wrmsr(i, msr); } //[4G, TOM2) - if(tom2_k) { + if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB @@ -1794,8 +1794,8 @@ static unsigned get_htic_bit(unsigned i, unsigned bit) static void wait_till_sysinfo_in_ram(void) { - while(1) { - if(get_htic_bit(0, 9)) return; + while (1) { + if (get_htic_bit(0, 9)) return; } } #endif @@ -1909,26 +1909,26 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; fill_mem_cs_sysinfo(i, ctrl+i, sysinfo); } tsc[0] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); - if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; + if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); } @@ -1938,28 +1938,28 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc #endif tsc[2] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); - if(train_DqsPos(ctrl+i, sysinfo)) goto out; + if (train_DqsPos(ctrl+i, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); } tsc[3] = rdtsc(); - for(i = 0; i < controllers; i++) { + for (i = 0; i < controllers; i++) { if (!sysinfo->ctrl_present[i]) continue; /* Skip everything if I don't have any memory on this controller */ - if(sysinfo->meminfo[i].dimm_mask==0x00) continue; + if (sysinfo->meminfo[i].dimm_mask==0x00) continue; printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); - if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; + if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; #if CONFIG_HAVE_ACPI_RESUME @@ -1972,7 +1972,7 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); - for(i=0;i<5;i++) { + for (i=0;i<5;i++) { print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo); } @@ -1992,7 +1992,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info tsc_t tsc[4]; - if(sysinfo->mem_trained[i] != 0x80) return; + if (sysinfo->mem_trained[i] != 0x80) return; #if CONFIG_MEM_TRAIN_SEQ == 1 //need to enable mtrr, so dqs training could access the test address @@ -2001,39 +2001,39 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info fill_mem_cs_sysinfo(i, ctrl, sysinfo); - if(v) { + if (v) { tsc[0] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i); } - if(train_DqsRcvrEn(ctrl, 1, sysinfo)) { + if (train_DqsRcvrEn(ctrl, 1, sysinfo)) { sysinfo->mem_trained[i]=0x81; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[1] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } - if(train_DqsPos(ctrl, sysinfo)) { + if (train_DqsPos(ctrl, sysinfo)) { sysinfo->mem_trained[i]=0x82; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[2] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ + if (train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // goto out; } - if(v) { + if (v) { printk(BIOS_DEBUG, " done\n"); tsc[3] = rdtsc(); @@ -2044,13 +2044,13 @@ out: clear_mtrr_dqs(sysinfo->tom2_k); #endif - if(v) { - for(ii=0;ii<4;ii++) { + if (v) { + for (ii=0;ii<4;ii++) { print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } } - if(sysinfo->mem_trained[i] == 0x80) { + if (sysinfo->mem_trained[i] == 0x80) { sysinfo->mem_trained[i]=1; } @@ -2069,7 +2069,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { - if(coreid) return; // only do it on core0 + if (coreid) return; // only do it on core0 struct sys_info *sysinfox; uintptr_t migrated_base = CONFIG_RAMTOP - car_data_size(); @@ -2077,7 +2077,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy wait_till_sysinfo_in_ram(); // use pci to get it - if(sysinfox->mem_trained[nodeid] == 0x80) { + if (sysinfox->mem_trained[nodeid] == 0x80) { #if 0 sysinfo->tom_k = sysinfox->tom_k; sysinfo->tom2_k = sysinfox->tom2_k; diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index 87e281d645..597b689f7c 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -96,7 +96,7 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value) #define PCI_DEV_INVALID (0xffffffffU) static device_t pci_locate_device(unsigned pci_id, device_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { @@ -131,7 +131,7 @@ unsigned long log2(unsigned long x) write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1); hlt(); } - for(; i > x; i >>= 1, pow--) + for (; i > x; i >>= 1, pow--) ; return pow; @@ -410,7 +410,7 @@ done: static void test2(void) { int i; - for(i = 0; i < 0x48; i++) { + for (i = 0; i < 0x48; i++) { do_test2(i); } diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 81da5920cb..cfc5dda718 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -57,7 +57,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { u8 reg; - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); if ((config_map & 3) != 3) { diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index 230459ab7f..f8f2bbfe70 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -8,7 +8,7 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns #if RES_DEBUG printk(BIOS_DEBUG, "setting up resource map offset....\n"); #endif - for(i = 0; i < max; i += 3) { + for (i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg = 0; @@ -46,7 +46,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int #if RES_DEBUG printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); #endif - for(i = 0; i < max; i += 4) { + for (i = 0; i < max; i += 4) { #if RES_DEBUG printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], @@ -128,7 +128,7 @@ static void setup_io_resource_map(const unsigned int *register_values, int max) { int i; - for(i = 0; i < max; i += 3) { + for (i = 0; i < max; i += 3) { unsigned where; unsigned long reg; @@ -163,7 +163,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max) { int i; - for(i = 0; i < max; i += 3) { + for (i = 0; i < max; i += 3) { unsigned where; unsigned long reg; #if 0 diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl index febfd2958e..6a9b69f267 100644 --- a/src/northbridge/amd/amdk8/util.asl +++ b/src/northbridge/amd/amdk8/util.asl @@ -54,7 +54,7 @@ Scope (\_SB) Method (GHCE, 1, NotSerialized) // check if the HC enabled { Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) - if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } Else { Return (0x00) } } |