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| author | Yinghai Lu <yinghailu@gmail.com> | 2005-12-14 20:16:49 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-12-14 20:16:49 +0000 |
| commit | 30576601f6d29a72d5057ac0051ebe3479abc03c (patch) | |
| tree | bc2a673d488c2993d619c1ab91ede0385617171f /src/northbridge/amd/amdk8 | |
| parent | 6f63c0297c3e3f31674dbbf193635921b5c20e15 (diff) | |
| download | coreboot-30576601f6d29a72d5057ac0051ebe3479abc03c.tar.xz | |
from issue 53: don't set TOM2 if 4G less mem installed, opt for init_ecc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index bd9ce2cd4f..c6a649a883 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -882,9 +882,11 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) /* Now set top of memory */ msr_t msr; - msr.lo = (tom_k & 0x003fffff) << 10; - msr.hi = (tom_k & 0xffc00000) >> 22; - wrmsr(TOP_MEM2, msr); + if(tom_k>(4*1024*1024)) { + msr.lo = (tom_k & 0x003fffff) << 10; + msr.hi = (tom_k & 0xffc00000) >> 22; + wrmsr(TOP_MEM2, msr); + } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 * so I can see my rom chip and other I/O devices. |