diff options
author | Stefan Reinauer <stepan@openbios.org> | 2005-11-26 16:56:05 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2005-11-26 16:56:05 +0000 |
commit | f622d598db3a6fb7001b6b63e7184272eb19db72 (patch) | |
tree | 568d3113d95e791baa444ed1904c8e88bc803601 /src/northbridge/amd/amdk8 | |
parent | b7627bca656d365615dbf2c06053430e83565f8d (diff) | |
download | coreboot-f622d598db3a6fb7001b6b63e7184272eb19db72.tar.xz |
- Apply 11_24_a_s1_core.diff from
https://openbios.org/roundup/linuxbios/issue24
- fix up for via epia-m
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8')
-rw-r--r-- | src/northbridge/amd/amdk8/Config.lb | 8 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/amdk8_acpi.c | 179 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/get_sblk_pci1234.c | 214 | ||||
-rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 13 |
4 files changed, 410 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb index 35b137068b..23245a66b9 100644 --- a/src/northbridge/amd/amdk8/Config.lb +++ b/src/northbridge/amd/amdk8/Config.lb @@ -1,5 +1,7 @@ uses CONFIG_CHIP_NAME uses AGP_APERTURE_SIZE +uses HAVE_ACPI_TABLES + default AGP_APERTURE_SIZE=0x4000000 if CONFIG_CHIP_NAME @@ -14,3 +16,9 @@ makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c" action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end + +if HAVE_ACPI_TABLES + object amdk8_acpi.o +end + +object get_sblk_pci1234.o diff --git a/src/northbridge/amd/amdk8/amdk8_acpi.c b/src/northbridge/amd/amdk8/amdk8_acpi.c new file mode 100644 index 0000000000..71bcdbbd1a --- /dev/null +++ b/src/northbridge/amd/amdk8/amdk8_acpi.c @@ -0,0 +1,179 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// + +/* + * 2005.9 yhlu add madt lapic creat dynamically and SRAT related + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +//it seems these function can be moved arch/i386/boot/acpi.c + +unsigned long acpi_create_madt_lapics(unsigned long current) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); + cpu_index++; + + } + + return current; +} + +unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); + cpu_index++; + + } + + return current; +} +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); + cpu_index++; + + } + + return current; +} + +static unsigned long resk(uint64_t value) +{ + unsigned long resultk; + if (value < (1ULL << 42)) { + resultk = value >> 10; + } + else { + resultk = 0xffffffff; + } + return resultk; +} + + +struct acpi_srat_mem_state { + unsigned long current; +}; + +void set_srat_mem(void *gp, struct device *dev, struct resource *res) +{ + struct acpi_srat_mem_state *state = gp; + unsigned long basek, sizek; + basek = resk(res->base); + sizek = resk(res->size); + + printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", + dev_path(dev), res->index, basek, sizek); + /* + 0-640K must be on node 0 + next range is from 1M--- + So will cut off before 1M in the mem range + */ + if((basek+sizek)<1024) return; + + if(basek<1024) { + sizek -= 1024 - basek; + basek = 1024; + } + + state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV +} + + +unsigned long acpi_fill_srat(unsigned long current) +{ + struct acpi_srat_mem_state srat_mem_state; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + /* create all subteble for memory range */ + + /* 0-640K must be on node 0 */ + current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable +#if 1 + srat_mem_state.current = current; + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + set_srat_mem, &srat_mem_state); + + current = srat_mem_state.current; +#endif + return current; +} +//end + diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c new file mode 100644 index 0000000000..d52a7f761a --- /dev/null +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -0,0 +1,214 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +// 2005.9 serengeti support +// by yhlu +// 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> + + +#if 0 +unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} +#endif + + +extern unsigned pci1234[]; +extern unsigned hc_possible_num; +extern unsigned sblk; + +/* why we need pci1234 array + final result for pci1234 will be + pci1234[0] will record sblink and bus range + pci1234[i] will record ht chain i. + it will keep the sequence when some ht io card is not installed. + + for Tyan S2885 the linxbios_ram will put 8151 chain (link 0) to 0xE0 reg, and 8131/8111 on 0xe4 reg, So we need to make sure the sb link + will always on pci1234[0] + for multi ht-io cards, if you don't install htio1, and only installed htio2, htio3, the htio will be on 0xe4, and 0xe8. + but we want to leave pci1234[1] to htio1 (even it is disabled) , and let htio2 and htio3 still use pci1234[2] and pci1234[3] + So we keep the sequence. ---- you need to preset the pci1234[1], pci1234[2], pci1234[3] for this purpose + for example you need set + unsigned pci1234[] = { + 0x0000ff0, + 0x0000f10, // HT IO 1 card always on node 1 + 0x0000f20, // HT IO 2 card always on node 2 + 0x0000f30 // HT IO 3 card always on node 3 + }; + + for 2p+htio(n1)+htio(n0_1)+htio(n1_1),2p+htio(n1)+2p+htio(n2)+htio(n3) : need pci1234[6] + unsigned pci1234[] = { + 0x0000ff0, + 0x0000010, // HT IO 1 card always on node 1 + 0x0000f00, // HT IO 2 card always on node 0 + 0x0000110, // HT IO 3 card always on node 1 + 0x0000f20, // HT IO 4 card always on node 2 + 0x0000f30 // HT IO 5 card always on node 3 + }; + + for 4p+htio(n1)+htio(n2)+htio(n3),4p+htio(n1)+4p+htio(n6)+htio(n7) : need pci1234[6] + unsigned pci1234[] = { + 0x0000ff0, + 0x0000f10, // HT IO 1 card always on node 1 + 0x0000f20, // HT IO 2 card always on node 2 + 0x0000f30, // HT IO 3 card always on node 3 + 0x0000f60, // HT IO 4 card always on node 6 + 0x0000f70 // HT IO 5 card always on node 7 + }; + + + for 2p+htio(n1)+htio(n0_1)+htio(n1_1), 2p+htio(n1)+2p+htio(n2)+htio(n3), 2p+htio(n1)+4p+htio(n4)+htio(n5), need pci1234[8] + unsigned pci1234[] = { + 0x0000ff0, + 0x0000010, // HT IO 1 card always on node 1 + 0x0000f00, // HT IO 2 card always on node 0 + 0x0000110, // HT IO 3 card always on node 1 + 0x0000f20, // HT IO 4 card always on node 2 + 0x0000f30 // HT IO 5 card always on node 3 + 0x0000f40, // HT IO 6 card always on node 4 + 0x0000f50 // HT IO 7 card always on node 5 + }; + + + for 4p+htio(n1)+htio(n2)+htio(n3), 4p+htio(n1)+2p+htio(n4)+htio(n5), 4p+htio(n1)+4p+htio(n6)+htio(n7), need pci1234[8] + unsigned pci1234[] = { + 0x0000ff0, + 0x0000f10, // HT IO 1 card always on node 1 + 0x0000f20, // HT IO 2 card always on node 2 + 0x0000f30, // HT IO 3 card always on node 3 + 0x0000f40, // HT IO 4 card always on node 4 + 0x0000f50 // HT IO 5 card always on node 5 + 0x0000f60, // HT IO 6 card always on node 6 + 0x0000f70 // HT IO 7 card always on node 7 + }; + + + So Max HC_POSSIBLE_NUM is 8 + + just put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c on MB dir + + Also don't forget to increase the ACPI_SSDTX_NUM etc if you have too much SSDT + + How about co-processor on socket 1 on 2 way system. or socket 2, and socket3 on 4 way system....? treat that as one hc too! + +*/ +void get_sblk_pci1234(void) +{ + + device_t dev; + int i,j; + uint32_t dword; + + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + dword = pci_read_config32(dev, 0x64); + sblk = (dword>>8) & 0x3; + + dword &=0x0300; + dword |= 1; + pci1234[0] = dword; + + /*about hardcode numbering for HT_IO support + set the node_id and link_id that could have ht chain in the one array, + then check if is enabled.... then update final value + */ + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + for(j=0;j<4;j++) { + uint32_t dwordx; + dwordx = pci_read_config32(dev, 0xe0+j*4); + dwordx &=0xffff0ff1; //keep bus num, node_id, link_num, enable bits + if((dwordx & 0xff1) == dword) { //SBLINK + pci1234[0] = dwordx; + continue; + } + if((dwordx & 1) == 1) { + // We need to find out the number of HC + // for exact match + for(i=1;i<hc_possible_num;i++) { + if((dwordx & 0xff0) == (pci1234[i] & 0xff0)) { + pci1234[i] = dwordx; + break; + } + } + // for 0xff0 match or same node + for(i=1;i<hc_possible_num;i++) { + if((dwordx & 0xff0) == (dwordx & pci1234[i] & 0xff0)) { + pci1234[i] = dwordx; + break; + } + } + } + } + + for(i=1;i<hc_possible_num;i++) { + if((pci1234[i] & 1) != 1) { + pci1234[i] = 0; + } + } + +} + diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 7ef1266130..14593d7f43 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -692,7 +692,7 @@ static void pci_domain_set_resources(device_t dev) /* Round mmio_basek to something the processor can support */ mmio_basek &= ~((1 << 6) -1); - idx = 10; + idx = 0x10; for(i = 0; i < 8; i++) { uint32_t base, limit; unsigned basek, limitk, sizek; @@ -708,7 +708,8 @@ static void pci_domain_set_resources(device_t dev) /* see if we need a hole from 0xa0000 to 0xbffff */ if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, idx++, basek, ((8*64)+(8*16)) - basek); + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; basek = (8*64)+(16*16); sizek = limitk - ((8*64)+(16*16)); @@ -720,7 +721,8 @@ static void pci_domain_set_resources(device_t dev) if (basek < mmio_basek) { unsigned pre_sizek; pre_sizek = mmio_basek - basek; - ram_resource(dev, idx++, basek, pre_sizek); + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; sizek -= pre_sizek; if(! is_cpu_pre_e0() ) { sizek += hoist_memory(mmio_basek,i); @@ -735,7 +737,8 @@ static void pci_domain_set_resources(device_t dev) sizek -= (4*1024*1024 - mmio_basek); } } - ram_resource(dev, idx++, basek, sizek); + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; } assign_resources(&dev->link[0]); } @@ -838,6 +841,8 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) /* Report what I have done */ if (cpu) { + cpu->path.u.apic.node_id = i; + cpu->path.u.apic.core_id = 0; printk_debug("CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); } |