diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/amdmct/mct/mct_d.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 4267e6d07c..2488dfc22b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,9 +33,9 @@ * supported. */ -#include "mct_d.h" - #include <string.h> +#include <cpu/amd/msr.h> +#include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -3686,7 +3686,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); lo |= 1 << ClLinesToNbDis; _WRMSR(msr, lo, hi); @@ -3703,7 +3703,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) lo &= ~(1 << ClLinesToNbDis); @@ -3721,7 +3721,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi |= (1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3737,7 +3737,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi &= ~(1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3845,7 +3845,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, return; } - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; @@ -3877,7 +3877,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } if (!wrap32dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); |