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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 15:46:49 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-20 19:08:30 +0000
commitffcac3eb502bbe0acbb30d6fe804f00e07461a7a (patch)
treed5deda572bb252a683a5ece24a5c4916ee198836 /src/northbridge/amd/amdmct/mct/mct_d_gcc.h
parent1ca978ee6529251ed80b47da679be7adc75fa46a (diff)
downloadcoreboot-ffcac3eb502bbe0acbb30d6fe804f00e07461a7a.tar.xz
nb/amd/fam10: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mct_d_gcc.h')
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d_gcc.h48
1 files changed, 0 insertions, 48 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
deleted file mode 100644
index 993aa21d74..0000000000
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MCT_D_GCC_H
-#define MCT_D_GCC_H
-
-#include <stdint.h>
-
-void _WRMSR(u32 addr, u32 lo, u32 hi);
-void _RDMSR(u32 addr, u32 *lo, u32 *hi);
-void _RDTSC(u32 *lo, u32 *hi);
-void _cpu_id(u32 addr, u32 *val);
-u32 bsr(u32 x);
-u32 bsf(u32 x);
-
-#define _MFENCE asm volatile ("mfence")
-#define _SFENCE asm volatile ("sfence")
-
-/* prevent speculative execution of following instructions */
-#define _EXECFENCE asm volatile ("outb %al, $0xed")
-
-u32 SetUpperFSbase(u32 addr_hi);
-void proc_CLFLUSH(u32 addr_hi);
-void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num);
-u32 read32_fs(u32 addr_lo);
-void FlushDQSTestPattern_L9(u32 addr_lo);
-__attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo);
-void ReadL18TestPattern(u32 addr_lo);
-void ReadL9TestPattern(u32 addr_lo);
-void ReadMaxRdLat1CLTestPattern_D(u32 addr);
-void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr);
-void FlushMaxRdLatTestPattern_D(u32 addr);
-u32 stream_to_int(u8 const *p);
-u8 oemNodePresent_D(u8 Node, u8 *ret);
-
-#endif