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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/amdmct/mct/mctsrc.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctsrc.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a29f8eb42e..4689c7b982 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include <cpu/x86/cr.h> +#include <cpu/amd/msr.h> +#include "mct_d.h" /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT @@ -170,7 +171,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, write_cr4(cr4); print_t("TrainRcvrEn: 2\n"); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); //FIXME: Why use SSEDIS if (lo & (1 << 17)) { /* save the old value */ @@ -443,7 +444,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); |