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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-09 18:55:58 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2018-08-10 21:25:53 +0000 |
commit | 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch) | |
tree | 7b5096ca1f81fecf70418020aba184e446f995e0 /src/northbridge/amd/amdmct/mct | |
parent | 1895838e7a3807a6fce324f0dfed193a3821f6df (diff) | |
download | coreboot-3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d.tar.xz |
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mctecc_d.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 18774ebe7a..7be63533a9 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -68,7 +68,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the * scrubber is used in two steps. First, the Dram Limit for the node is adjusted * down to the bottom of the gap, and that ECC dram is initialized. Second, the - * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is + * original Limit is restored, the Scrub base is set to 4GB, and scrubber is * allowed to run until the Scrub Addr wraps around to zero. */ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) |