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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-26 20:17:50 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-02 16:14:36 +0000 |
| commit | 63f98f23045e072b0d07ecdd4cd50d01ad844df7 (patch) | |
| tree | cd0cff2a76b8b44b9563de0cf63f2e8b831e9735 /src/northbridge/amd/amdmct/mct | |
| parent | 7803e487bdd64ec0f1a8a17a483a4298d38bb77a (diff) | |
| download | coreboot-63f98f23045e072b0d07ecdd4cd50d01ad844df7.tar.xz | |
src: Use CRx_TYPE type for CRx
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 36ee3ab332..2e52a39619 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -278,7 +278,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, u8 dqsWrDelay_end; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 649c1c85c2..406547e0f8 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -129,7 +129,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index a78d42df85..6ec4d648d8 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -122,7 +122,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 PatternBuffer[60]; // FIXME: why not 48 + 4 u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; |