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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-09-05 18:56:05 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-02 23:26:41 +0100 |
| commit | 2a83935d9f50e3059e7747338a700c2fceb1731a (patch) | |
| tree | b40831293a339c6743ec86e7820111c38c536113 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
| parent | 65eec4d959a847c43b5f4e92c6eee60f042fd7f6 (diff) | |
| download | coreboot-2a83935d9f50e3059e7747338a700c2fceb1731a.tar.xz | |
northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11957
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index d40381702b..146e699a56 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -202,6 +202,7 @@ #define JED_MiniRDIMM 0x5 /* Mini-RDIMM */ #define SPD_Density 4 /* Bank address bits,SDRAM capacity */ #define SPD_Addressing 5 /* Row/Column address bits */ +#define SPD_Voltage 6 /* Supported voltage bitfield */ #define SPD_Organization 7 /* rank#,Device width */ #define SPD_BusWidth 8 /* ECC, Bus width */ #define JED_ECC 8 /* ECC capability */ @@ -581,6 +582,10 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ + /* DIMM supported voltage bitmap ([2:0]: 1.25V, 1.35V, 1.5V) */ + uint8_t DimmSupportedVoltages[MAX_DIMMS_SUPPORTED]; + uint32_t DimmConfiguredVoltage[MAX_DIMMS_SUPPORTED]; /* mV */ + uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; @@ -901,6 +906,7 @@ u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); void mctSMBhub_Init(u32 node); +void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); |