diff options
author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-08 14:00:48 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-10 17:22:33 +0100 |
commit | a4dcdca7ba4ef771272a1010be0268c8cf697058 (patch) | |
tree | 1e749257aa340661516d3a7fa9034a2b1c82e891 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
parent | 8c42424ec1669036fb4a7be4eb7ec0915bd6966c (diff) | |
download | coreboot-a4dcdca7ba4ef771272a1010be0268c8cf697058.tar.xz |
amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc
Several members of DCTStatStruc are designed to persist across resets of
all other members. Move the persistent members into a substructure in
order to simplify the reset logic and avoid compiler warnings / UB.
Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18058
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 575a9d61bf..d4b37921c4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Raptor Engineering, LLC + * Copyright (C) 2015-2017 Raptor Engineering, LLC * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -335,6 +335,20 @@ struct amd_spd_node_data { uint8_t nvram_memclk[2]; /* [channel] */ } __attribute__((packed, aligned(4))); +struct DCTPersistentStatStruc { + u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM0 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHA DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM0 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + /* CHB DIMM1 Byte 0 - 7 TxDqs */ + u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ + u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ +} __attribute__((packed, aligned(4))); + struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ u8 Node_ID; /* Node ID of current controller */ @@ -485,8 +499,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/ /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/ uint64_t LogicalCPUID; /* The logical CPUID of the node*/ - u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ - u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ u16 DimmQRPresent; /* QuadRank DIMM present?*/ u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/ u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/ @@ -513,15 +525,6 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/ /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/ /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/ - u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM0 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHA DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM0 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ - /* CHB DIMM1 Byte 0 - 7 TxDqs */ u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ /* CHA DIMM 0 Receiver Enable Delay*/ /* CHA DIMM 1 Receiver Enable Delay*/ @@ -635,6 +638,9 @@ struct DCTStatStruc { /* A per Node structure*/ uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; struct amd_spd_node_data spd_data; + + /* NOTE: This must remain the last entry in this structure */ + struct DCTPersistentStatStruc persistentData; } __attribute__((packed, aligned(4))); struct amd_s3_persistent_mct_channel_data { |