diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-09-05 17:55:58 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-10-26 23:52:54 +0100 |
| commit | b8a355dcdf319671b97f8688209ad5d471fc0905 (patch) | |
| tree | 6cd55b06343af460642431bb8dd3d782d0ccc45e /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
| parent | 7a5413a81c2fecc443999b006d641cd903327346 (diff) | |
| download | coreboot-b8a355dcdf319671b97f8688209ad5d471fc0905.tar.xz | |
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
The native AMD DDR3 memory initialization code was riddled with
numerous errors and was missing critical configuration code segments;
this made it so that DDR3 memory did not function on most AMD boards.
This patch corrects enough of the DDR3 initialization such that
UDIMMs can be used on most channels of G34 Opteron boards. Further
work is needed to fix the broken RDIMM code and remaining UDIMM issues.
Change-Id: Iab690db769e820600693ad1170085623b177b94e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11941
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index d6e5fb4ca9..987c0c8a5c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -499,7 +499,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM0 Byte 0 - 7 TxDqs */ /* CHB DIMM1 Byte 0 - 7 TxDqs */ /* CHB DIMM1 Byte 0 - 7 TxDqs */ - u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ + u16 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */ /* CHA DIMM 0 Receiver Enable Delay*/ /* CHA DIMM 1 Receiver Enable Delay*/ /* CHA DIMM 2 Receiver Enable Delay*/ @@ -509,7 +509,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* CHB DIMM 1 Receiver Enable Delay*/ /* CHB DIMM 2 Receiver Enable Delay*/ /* CHB DIMM 3 Receiver Enable Delay*/ - u8 CH_D_BC_RCVRDLY[2][4]; + u16 CH_D_BC_RCVRDLY[2][4]; /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/ /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/ @@ -769,7 +769,7 @@ u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass); u32 SetupDqsPattern_1PassA(u8 Pass); u32 SetupDqsPattern_1PassB(u8 Pass); u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass); -u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass); +u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u16 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass); void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); uint64_t mctGetLogicalCPUID(u32 Node); @@ -779,7 +779,7 @@ void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA); -void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass); +void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass); void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel); void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct); void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct); |