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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-09-05 17:55:58 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2015-10-26 23:52:54 +0100 |
commit | b8a355dcdf319671b97f8688209ad5d471fc0905 (patch) | |
tree | 6cd55b06343af460642431bb8dd3d782d0ccc45e /src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | |
parent | 7a5413a81c2fecc443999b006d641cd903327346 (diff) | |
download | coreboot-b8a355dcdf319671b97f8688209ad5d471fc0905.tar.xz |
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
The native AMD DDR3 memory initialization code was riddled with
numerous errors and was missing critical configuration code segments;
this made it so that DDR3 memory did not function on most AMD boards.
This patch corrects enough of the DDR3 initialization such that
UDIMMs can be used on most channels of G34 Opteron boards. Further
work is needed to fix the broken RDIMM code and remaining UDIMM issues.
Change-Id: Iab690db769e820600693ad1170085623b177b94e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11941
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 87 |
1 files changed, 22 insertions, 65 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index 60f98bc89a..9990304645 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -103,10 +104,10 @@ static void proc_CLFLUSH(u32 addr_hi) __asm__ volatile ( /* clflush fs:[eax] */ - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "clflush %%fs:(%0)\n\t" + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "clflush %%fs:(%0)\n\t" "mfence\n\t" - ::"a" (addr_hi<<8) + ::"a" (addr_hi<<8) ); } @@ -141,6 +142,24 @@ static u32 read32_fs(u32 addr_lo) return value; } +static uint64_t read64_fs(uint32_t addr_lo) +{ + uint64_t value = 0; + uint32_t value_lo; + uint32_t value_hi; + + __asm__ volatile ( + "outb %%al, $0xed\n\t" /* _EXECFENCE */ + "mfence\n\t" + "movl %%fs:(%2), %0\n\t" + "movl %%fs:(%3), %1\n\t" + :"=c"(value_lo), "=d"(value_hi): "a" (addr_lo), "b" (addr_lo + 4) : "memory" + ); + value |= value_lo; + value |= ((uint64_t)value_hi) << 32; + return value; +} + #ifdef UNUSED_CODE static u8 read8_fs(u32 addr_lo) { @@ -210,68 +229,6 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(u32 addr_lo) ); } -static void ReadL18TestPattern(u32 addr_lo) -{ - /* set fs and use fs prefix to access the mem */ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - "movl %%fs:-128(%%esi), %%eax\n\t" /* TestAddr cache line */ - "movl %%fs:-64(%%esi), %%eax\n\t" /* +1 */ - "movl %%fs:(%%esi), %%eax\n\t" /* +2 */ - "movl %%fs:64(%%esi), %%eax\n\t" /* +3 */ - - "movl %%fs:-128(%%edi), %%eax\n\t" /* +4 */ - "movl %%fs:-64(%%edi), %%eax\n\t" /* +5 */ - "movl %%fs:(%%edi), %%eax\n\t" /* +6 */ - "movl %%fs:64(%%edi), %%eax\n\t" /* +7 */ - - "movl %%fs:-128(%%ebx), %%eax\n\t" /* +8 */ - "movl %%fs:-64(%%ebx), %%eax\n\t" /* +9 */ - "movl %%fs:(%%ebx), %%eax\n\t" /* +10 */ - "movl %%fs:64(%%ebx), %%eax\n\t" /* +11 */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" /* +12 */ - "movl %%fs:-64(%%ecx), %%eax\n\t" /* +13 */ - "movl %%fs:(%%ecx), %%eax\n\t" /* +14 */ - "movl %%fs:64(%%ecx), %%eax\n\t" /* +15 */ - - "movl %%fs:-128(%%edx), %%eax\n\t" /* +16 */ - "movl %%fs:-64(%%edx), %%eax\n\t" /* +17 */ - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c" (addr_lo+128+12*64), - "d" (addr_lo +128+16*64), "S"(addr_lo+128), - "D"(addr_lo+128+4*64) - ); - -} - -static void ReadL9TestPattern(u32 addr_lo) -{ - - /* set fs and use fs prefix to access the mem */ - __asm__ volatile ( - "outb %%al, $0xed\n\t" /* _EXECFENCE */ - - "movl %%fs:-128(%%ecx), %%eax\n\t" /* TestAddr cache line */ - "movl %%fs:-64(%%ecx), %%eax\n\t" /* +1 */ - "movl %%fs:(%%ecx), %%eax\n\t" /* +2 */ - "movl %%fs:64(%%ecx), %%eax\n\t" /* +3 */ - - "movl %%fs:-128(%%edx), %%eax\n\t" /* +4 */ - "movl %%fs:-64(%%edx), %%eax\n\t" /* +5 */ - "movl %%fs:(%%edx), %%eax\n\t" /* +6 */ - "movl %%fs:64(%%edx), %%eax\n\t" /* +7 */ - - "movl %%fs:-128(%%ebx), %%eax\n\t" /* +8 */ - "mfence\n\t" - - :: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), - "d"(addr_lo+128+4*64) - ); - -} - static void ReadMaxRdLat1CLTestPattern_D(u32 addr) { SetUpperFSbase(addr); |