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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-16 13:51:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-02 23:45:19 +0100 |
| commit | 730a043fb6cb4dd3cb5af8f8640365727b598648 (patch) | |
| tree | 59afe45caca1a8e1682939c7e44e95344104533e /src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c | |
| parent | d150006c4a4584bc9933c2d8ff580a54c4f0cc2a (diff) | |
| download | coreboot-730a043fb6cb4dd3cb5af8f8640365727b598648.tar.xz | |
cpu/amd: Add initial AMD Family 15h support
TEST: Booted ASUS KGPE-D16 with single Opteron 6380
* Unbuffered DDR3 DIMMs tested and working
* Suspend to RAM (S3) tested and working
Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c index 1700cf76b5..93d2800b00 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,6 +14,8 @@ * GNU General Public License for more details. */ +/* AM3/ASB2/C32/G34 DDR3 */ + static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode); @@ -20,17 +23,23 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) { - Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, - pDCTstat->MAload[dct], - &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), - &pDCTstat->_2Tmode); + if (is_fam15h()) { + pDCTstat->CH_ADDR_TMG[dct] = fam15h_address_timing_compensation_code(pDCTstat, dct); + pDCTstat->CH_ODC_CTL[dct] = fam15h_output_driver_compensation_code(pDCTstat, dct); + pDCTstat->_2Tmode = fam15h_slow_access_mode(pDCTstat, dct); + } else { + Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, + pDCTstat->MAload[dct], + &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), + &pDCTstat->_2Tmode); + + pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 60ohms */ + } pDCTstat->CH_EccDQSLike[0] = 0x0403; pDCTstat->CH_EccDQSScale[0] = 0x70; pDCTstat->CH_EccDQSLike[1] = 0x0403; pDCTstat->CH_EccDQSScale[1] = 0x70; - - pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 60ohms */ } /* |