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author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-27 19:37:31 +0200 |
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committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 04:40:27 +0200 |
commit | 0f92f630556b4bf2e4c0696cae4c2f8e97eda334 (patch) | |
tree | b97ad7a89a101c4770774035db5e4693043be928 /src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | |
parent | 081651b6677c64a5f2861d831822b5f8f3517c21 (diff) | |
download | coreboot-0f92f630556b4bf2e4c0696cae4c2f8e97eda334.tar.xz |
Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 76d01dadb2..d7084ad385 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -668,8 +668,8 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, /* When 400, 533, 667, it will support dimm0/1/2/3, * and set conf for dimm0, hw will copy to dimm1/2/3 * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800Mhz and above + 0x100 to next dimm + * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm + * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm */ /* FindDQSDatDimmVal_D is not required since we use an array */ @@ -709,8 +709,8 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, /* When 400, 533, 667, it will support dimm0/1/2/3, * and set conf for dimm0, hw will copy to dimm1/2/3 * set for dimm1, hw will copy to dimm3 - * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm - * Rev C support DIMM0/1/2/3 when 800Mhz and above + 0x100 to next dimm + * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm + * Rev C support DIMM0/1/2/3 when 800MHz and above + 0x100 to next dimm */ /* FindDQSDatDimmVal_D is not required since we use an array */ |