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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-26 00:55:43 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:55:57 +0100 |
| commit | f682d0028cb33fc4a085af83344f4a7b9c0e78f2 (patch) | |
| tree | 84c2289b2ca976c728f2fb42ded31c9f79c7a275 /src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | |
| parent | 474ff3dee54e81017587f53ce644307e4f655333 (diff) | |
| download | coreboot-f682d0028cb33fc4a085af83344f4a7b9c0e78f2.tar.xz | |
amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots. ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.
Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 58 |
1 files changed, 37 insertions, 21 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 9dbdcfb99b..cdb93f9405 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -237,37 +237,53 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, u8 scale, u8 ChipSel) { - u8 DQSDelay0, DQSDelay1; - u16 DQSDelay; + uint8_t DQSDelay0, DQSDelay1; + int16_t delay_differential; + uint16_t DQSDelay; if (pDCTstat->Status & (1 << SB_Registered)) { - return; - } + pDCTstat->ByteLane = 0x2; + GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); + DQSDelay0 = pDCTstat->DQSDelay; - pDCTstat->ByteLane = like & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay0 = pDCTstat->DQSDelay; + pDCTstat->ByteLane = 0x3; + GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); + DQSDelay1 = pDCTstat->DQSDelay; - pDCTstat->ByteLane = (like >> 8) & 0xff; - GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); - DQSDelay1 = pDCTstat->DQSDelay; + if (pDCTstat->Direction == DQS_READDIR) { + DQSDelay = DQSDelay1; + } else { + delay_differential = (int16_t)DQSDelay1 - (int16_t)DQSDelay0; + delay_differential += (int16_t)DQSDelay1; - if (DQSDelay0>DQSDelay1) { - DQSDelay = DQSDelay0 - DQSDelay1; + DQSDelay = delay_differential; + } } else { - DQSDelay = DQSDelay1 - DQSDelay0; - } + pDCTstat->ByteLane = like & 0xff; + GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); + DQSDelay0 = pDCTstat->DQSDelay; - DQSDelay = DQSDelay * (~scale); + pDCTstat->ByteLane = (like >> 8) & 0xff; + GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel); + DQSDelay1 = pDCTstat->DQSDelay; - DQSDelay += 0x80; /* round it */ + if (DQSDelay0>DQSDelay1) { + DQSDelay = DQSDelay0 - DQSDelay1; + } else { + DQSDelay = DQSDelay1 - DQSDelay0; + } - DQSDelay >>= 8; /* 256 */ + DQSDelay = DQSDelay * (~scale); - if (DQSDelay0>DQSDelay1) { - DQSDelay = DQSDelay1 - DQSDelay; - } else { - DQSDelay += DQSDelay1; + DQSDelay += 0x80; /* round it */ + + DQSDelay >>= 8; /* 256 */ + + if (DQSDelay0>DQSDelay1) { + DQSDelay = DQSDelay1 - DQSDelay; + } else { + DQSDelay += DQSDelay1; + } } pDCTstat->DQSDelay = (u8)DQSDelay; |