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author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | |
parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
download | coreboot-5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9.tar.xz |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index c0ae440a64..5d31849fb4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -152,12 +152,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); - if(pDCTstat->ErrCode != SC_RunningOK) { + if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); @@ -168,7 +168,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } else { AllECC = 0; } - if(LDramECC) { /* if ECC is enabled on this dram */ + if (LDramECC) { /* if ECC is enabled on this dram */ if (OB_NBECC) { mct_EnableDatIntlv_D(pMCTstat, pDCTstat); val = Get_NB32(pDCTstat->dev_dct, 0x110); @@ -194,7 +194,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* if Node present */ } - if(AllECC) + if (AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); @@ -210,7 +210,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -292,7 +292,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } - if(mctGet_NVbits(NV_SyncOnUnEccEn)) + if (mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); @@ -325,8 +325,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if((val & 3)==3) { /* Node has dram populated*/ - if( isDramECCEn_D(pDCTstat)) { + if ((val & 3)==3) { /* Node has dram populated*/ + if ( isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -348,16 +348,16 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) u8 ch_end; u8 isDimmECCEn = 0; - if(pDCTstat->GangedMode) { + if (pDCTstat->GangedMode) { ch_end = 1; } else { ch_end = 2; } - for(i=0; i<ch_end; i++) { - if(pDCTstat->DIMMValidDCT[i] > 0){ + for (i=0; i<ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0){ reg = 0x90; /* Dram Config Low */ val = Get_NB32_DCT(dev, i, reg); - if(val & (1<<DimmEcEn)) { + if (val & (1<<DimmEcEn)) { /* set local flag 'dram ecc capable' */ isDimmECCEn = 1; break; |