diff options
author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:11:47 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2016-01-24 23:20:31 +0100 |
commit | 6aa6eab98b37ae2d8878b2eb90c64478ab172b42 (patch) | |
tree | 7a0147b812a2dfb9316c1973a9248742abc5f26f /src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | |
parent | 19ce16ae69f31ef37c5edcbc3621a8060176b7e9 (diff) | |
download | coreboot-6aa6eab98b37ae2d8878b2eb90c64478ab172b42.tar.xz |
northbridge/amd/amdmct: Add termination and timing values for C32 sockets
The existing MCT initialization code was largely missing C32 socket-
specific configuration data. Add C32 socket-specific timing and ODT
values as specified in the BKDG.
Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13141
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 254 |
1 files changed, 254 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 143290f4be..822d813ef1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -117,6 +117,67 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d term = 0x2; } } + } else if (package_type == PT_C3) { + /* Socket C32: Fam15h BKDG v3.14 Table 60 */ + if (MaxDimmsInstallable == 1) { + if ((frequency_index == 0x4) || (frequency_index == 0x6) + || (frequency_index == 0xa) || (frequency_index == 0xe)) { + /* DDR3-667 - DDR3-1333 */ + if (rank_count < 3) + term = 0x0; + else + term = 0x2; + } else { + /* DDR3-1600 */ + term = 0x0; + } + } else if (MaxDimmsInstallable == 2) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if ((number_of_dimms == 1) && ((rank_count_dimm0 < 4) + && (rank_count_dimm1 < 4))) + term = 0x0; + else + term = 0x2; + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x0; + else + term = 0x2; + } else { + term = 0x1; + } + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + term = 0x2; + } else { + /* DDR3-1600 */ + if (number_of_dimms == 1) + term = 0x0; + else + term = 0x1; + } + } else if (MaxDimmsInstallable == 3) { + rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct]; + + if ((frequency_index == 0xa) || (frequency_index == 0xe)) { + /* DDR3-1066 - DDR3-1333 */ + if (rank_count_dimm2 < 4) + term = 0x1; + else + term = 0x2; + } else if (frequency_index == 0x12) { + /* DDR3-1600 */ + term = 0x1; + } else { + term = 0x2; + } + } } else { /* TODO * Other sockets unimplemented @@ -151,6 +212,33 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d term = 0x2; } } + } else if (package_type == PT_C3) { + /* Socket C32: Fam15h BKDG v3.14 Table 59 */ + if (MaxDimmsInstallable == 1) { + term = 0x0; + } else if (MaxDimmsInstallable == 2) { + if ((number_of_dimms == 2) && (frequency_index == 0x12)) { + term = 0x1; + } else if (number_of_dimms == 1) { + term = 0x0; + } else { + term = 0x2; + } + } else if (MaxDimmsInstallable == 3) { + if (number_of_dimms == 1) { + if (frequency_index <= 0xa) { + term = 0x2; + } else { + if (rank_count < 3) { + term = 0x1; + } else { + term = 0x2; + } + } + } else if (number_of_dimms == 2) { + term = 0x2; + } + } } else { /* TODO * Other sockets unimplemented @@ -302,6 +390,125 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t * 3 DIMM/channel support unimplemented */ } + } else if (package_type == PT_C3) { + /* Socket C32: Fam15h BKDG v3.14 Table 60 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if (rank_count_dimm0 < 4) { + term = 0x2; + } else { + if (!rank) + term = 0x2; + else + term = 0x0; + } + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + term = 0x1; + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + if (rank_count_dimm0 < 4) { + term = 0x1; + } else { + if (!rank) + term = 0x3; + else + term = 0x0; + } + } else { + term = 0x3; + } + } else if (MaxDimmsInstallable == 2) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x2; + else if (rank) + term = 0x0; + else + term = 0x2; + } else { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { + term = 0x3; + } else { + if (rank_count_dimm0 == 4) { + if (rank_count_dimm1 == 1) + term = 0x5; + else + term = 0x1; + } else if (rank_count_dimm1 == 4) { + if (rank_count_dimm0 == 1) + term = 0x5; + else + term = 0x1; + } + if (rank) + term = 0x0; + } + } + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x1; + else if (rank) + term = 0x0; + else + term = 0x1; + } else { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { + term = 0x3; + } else { + if (rank_count_dimm0 == 4) { + if (rank_count_dimm1 == 1) + term = 0x5; + else + term = 0x1; + } else if (rank_count_dimm1 == 4) { + if (rank_count_dimm0 == 1) + term = 0x5; + else + term = 0x1; + } + if (rank) + term = 0x0; + } + } + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x1; + else if (rank) + term = 0x0; + else + term = 0x3; + } else { + term = 0x5; + } + } else { + /* DDR3-1600 */ + if (number_of_dimms == 1) + term = 0x3; + else + term = 0x4; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } else { + /* TODO + * Other sockets unimplemented + */ } } else { /* UDIMM */ @@ -352,6 +559,53 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t } } } + } else if (package_type == PT_C3) { + /* Socket C32: Fam15h BKDG v3.14 Table 62 */ + if (MaxDimmsInstallable == 1) { + if ((frequency_index == 0x4) || (frequency_index == 0x6)) + term = 0x2; + else if ((frequency_index == 0xa) || (frequency_index == 0xe)) + term = 0x1; + else + term = 0x3; + } + if (MaxDimmsInstallable == 2) { + if (number_of_dimms == 1) { + if (frequency_index <= 0x6) { + term = 0x2; + } else if (frequency_index <= 0xe) { + term = 0x1; + } else { + term = 0x3; + } + } else { + if (frequency_index <= 0xa) { + term = 0x3; + } else if (frequency_index <= 0xe) { + term = 0x5; + } else { + term = 0x4; + } + } + } else if (MaxDimmsInstallable == 3) { + if (number_of_dimms == 1) { + term = 0x0; + } else if (number_of_dimms == 2) { + if (frequency_index <= 0xa) { + if (rank == 1) { + term = 0x0; + } else { + term = 0x3; + } + } else if (frequency_index <= 0xe) { + if (rank == 1) { + term = 0x0; + } else { + term = 0x5; + } + } + } + } } else { /* TODO * Other sockets unimplemented |