diff options
| author | Kerry She <Kerry.she@amd.com> | 2010-08-30 07:31:31 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-08-30 07:31:31 +0000 |
| commit | 99cfa1e6bdc7e89f571a52ed636704be894418d1 (patch) | |
| tree | 8ffc6930eaf5b13c106b18129923b63e59c6210f /src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | |
| parent | 108d30ba8652b27a2c78a0d5db22a445e272f396 (diff) | |
| download | coreboot-99cfa1e6bdc7e89f571a52ed636704be894418d1.tar.xz | |
Multi-DIMMS on AMD ddr3 MCT channel B works.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index d14bc0dd58..d4b531f3af 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -86,7 +86,7 @@ void PrepareC_DCT(struct MCTStatStruc *pMCTstat, for (dimm = 0; dimm < MAX_TOTAL_DIMMS; dimm++) { u8 DimmRanks; - if (DimmValid & (1 << dimm)) { + if (DimmValid & (1 << (dimm << 1))) { DimmRanks = 1; if (pDCTstat->DimmDRPresent & (1 << (dimm+dct))) DimmRanks = 2; |