diff options
author | Zheng Bao <zheng.bao@amd.com> | 2011-01-06 02:18:12 +0000 |
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committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-01-06 02:18:12 +0000 |
commit | 69436e1a8ccf50d67004f74360f3ff5e6a146b9a (patch) | |
tree | a1765936b1304bcc16aaba9dafe7ead509cf50ec /src/northbridge/amd/amdmct/mct_ddr3/modtrd.c | |
parent | da712f3f45bf27dc7326887c2d38cc7599f7448a (diff) | |
download | coreboot-69436e1a8ccf50d67004f74360f3ff5e6a146b9a.tar.xz |
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/modtrd.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/modtrd.c | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c new file mode 100644 index 0000000000..58ddf598ee --- /dev/null +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrd.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static u32 mct_MR1Odt_RDimm(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dct, u32 MrsChipSel) +{ + u8 Speed = pDCTstat->Speed; + u32 ret; + u8 DimmsInstalled, DimmNum, ChipSelect; + + ChipSelect = (MrsChipSel >> 20) & 0xF; + DimmNum = ChipSelect & 0xFE; + DimmsInstalled = pDCTstat->MAdimms[dct]; + if (dct == 1) + DimmNum ++; + ret = 0; + + if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { + if (DimmsInstalled == 1) + ret |= 1 << 2; + else { + if (pDCTstat->CSPresent & 0xF0) { + if (pDCTstat->DimmQRPresent & (1 << DimmNum)) { + if (!(ChipSelect & 1)) + ret |= 1 << 2; + } else + ret |= 0x204; + } else { + if (Speed < 6) + ret |= 0x44; + else + ret |= 0x204; + } + } + } else if (DimmsInstalled == 1) + ret |= 1 << 2; + else if (Speed < 6) + ret |= 0x44; + else + ret |= 0x204; + + //ret = 0; + return ret; +} + +static u32 mct_DramTermDyn_RDimm(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 dimm) +{ + u8 DimmsInstalled = dimm; + u32 DramTermDyn = 0; + u8 Speed = pDCTstat->Speed; + + if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { + if (pDCTstat->CSPresent & 0xF0) { + if (DimmsInstalled == 1) + if (Speed == 7) + DramTermDyn |= 1 << 10; + else + DramTermDyn |= 1 << 11; + else + if (Speed == 4) + DramTermDyn |= 1 << 11; + else + DramTermDyn |= 1 << 10; + } else { + if (DimmsInstalled != 1) { + if (Speed == 7) + DramTermDyn |= 1 << 10; + else + DramTermDyn |= 1 << 11; + } + } + } else { + if (DimmsInstalled != 1) + DramTermDyn |= 1 << 11; + } + return DramTermDyn; +} |