diff options
author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c | |
parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
download | coreboot-75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7.tar.xz |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c | 49 |
1 files changed, 28 insertions, 21 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index 18cad7eae7..f17e4d6758 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -15,22 +15,29 @@ */ /* This file contains functions for common utility functions */ +#include <inttypes.h> +#include <console/console.h> +#include <string.h> +#include "mct_d.h" +#include "mct_d_gcc.h" +#include "mwlc_d.h" -/* - *----------------------------------------------------------------------------- - * MODULES USED - * - *----------------------------------------------------------------------------- - */ +static uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} -static void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) +void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) { /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */ @@ -42,7 +49,7 @@ static void AmdMemPCIReadBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) *pValue &= (((u32)1 << (highbit-lowbit+1))-1); } -static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) +void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) { u32 temp, mask; @@ -72,7 +79,7 @@ static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) * OUT value = Target value with the bit set *----------------------------------------------------------------------------- */ -static u32 bitTestSet(u32 csMask,u32 tempD) +u32 bitTestSet(u32 csMask,u32 tempD) { u32 localTemp; /* ASSERT(tempD < 32); */ @@ -93,7 +100,7 @@ static u32 bitTestSet(u32 csMask,u32 tempD) * OUT value = Target value with the bit re-set *----------------------------------------------------------------------------- */ -static u32 bitTestReset(u32 csMask,u32 tempD) +u32 bitTestReset(u32 csMask,u32 tempD) { u32 temp, localTemp; /* ASSERT(tempD < 32); */ @@ -126,7 +133,7 @@ static u32 bitTestReset(u32 csMask,u32 tempD) * OUT value = Value read from PCI space *----------------------------------------------------------------------------- */ -static u32 get_Bits(sDCTStruct *pDCTData, +u32 get_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high) { @@ -200,7 +207,7 @@ static u32 get_Bits(sDCTStruct *pDCTData, * OUT *----------------------------------------------------------------------------- */ -static void set_Bits(sDCTStruct *pDCTData, +void set_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high, u32 value) { @@ -275,7 +282,7 @@ static void set_Bits(sDCTStruct *pDCTData, * OUT *------------------------------------------------- */ -static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, +u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high) { @@ -313,7 +320,7 @@ static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, * OUT *------------------------------------------------- */ -static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, +void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, u8 dct, u8 node, u8 func, u16 offset, u8 low, u8 high, u32 value) { @@ -348,7 +355,7 @@ static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, * FALSE - bit is clear *------------------------------------------------- */ -static BOOL bitTest(u32 value, u8 bitLoc) +BOOL bitTest(u32 value, u8 bitLoc) { u32 tempD, compD; tempD = value; |