diff options
author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | |
parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
download | coreboot-75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7.tar.xz |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/s3utils.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 8a726952dd..d13cb23c80 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -12,20 +12,20 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef S3UTILS_H +#define S3UTILS_H #include "../wrappers/mcti.h" #include "mct_d.h" -void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); -uint16_t calculate_nvram_mct_hash(void); - -#ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -#endif - #ifdef __RAMSTAGE__ int8_t save_mct_information_to_nvram(void); -#endif -int8_t restore_mct_information_from_nvram(uint8_t training_only); void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data); -void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only); +#endif + +void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); +void compare_nvram_spd_hashes(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat); + +#endif |