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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 10:56:26 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 15:52:09 +0000 |
commit | a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch) | |
tree | 4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/northbridge/amd/amdmct/mct_ddr3 | |
parent | 9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff) | |
download | coreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz |
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f62aa1568a..b62661b307 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -684,7 +684,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */ + /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */ tempW = tempW|((tempW1&0x00700000) >> 17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) |