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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-07-13 02:20:27 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-07-13 19:45:59 +0000 |
| commit | 6a00113de8b9060a7227bcfa79b3786e3e592a33 (patch) | |
| tree | 467f5653272ed2d16f6d8033ed8cd0e7391fb426 /src/northbridge/amd/amdmct | |
| parent | 9f244a5494192707bfbb72e60f17411e9a35434a (diff) | |
| download | coreboot-6a00113de8b9060a7227bcfa79b3786e3e592a33.tar.xz | |
Rename __attribute__((packed)) --> __packed
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index d13143d979..6a69cfae8c 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -23,6 +23,7 @@ #define DQS_TRAIN_DEBUG 0 #include <inttypes.h> +#include <compiler.h> #include "mct_d_gcc.h" #include <console/console.h> #include <northbridge/amd/amdfam10/debug.h> @@ -275,7 +276,7 @@ struct MCTStatStruc { of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ -} __attribute__((packed)); +} __packed; /*============================================================================= Global MCT Configuration Status Word (GStatus) @@ -321,7 +322,7 @@ struct DCTPersistentStatStruc { /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/ u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/ u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/ -} __attribute__((packed)); +} __packed; struct DCTStatStruc { /* A per Node structure*/ @@ -549,7 +550,7 @@ struct DCTStatStruc { /* A per Node structure*/ /* NOTE: This must remain the last entry in this structure */ struct DCTPersistentStatStruc persistentData; -} __attribute__((packed)); +} __packed; /*=============================================================================== Local Error Status Codes (DCTStatStruc.ErrCode) @@ -717,7 +718,7 @@ struct amdmct_memory_info { struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; uint16_t ecc_enabled; uint16_t ecc_scrub_rate; -} __attribute__((packed)); +} __packed; u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); |