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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-30 13:48:24 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-31 23:09:29 +0200 |
| commit | b3ddf83a118a7b1ae374ec00cd98420331f36cb1 (patch) | |
| tree | 0a55098f1b2eb454256ba113612af8dfdaad8690 /src/northbridge/amd/amdmct | |
| parent | e35db2c6eb66945d443f60ad2ba6e0e0fed27ad1 (diff) | |
| download | coreboot-b3ddf83a118a7b1ae374ec00cd98420331f36cb1.tar.xz | |
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Enabling sync flood on DRAM MCE directly after ECC clear can
lead to a system hang with no way to determine the offending
DRAM module. Clear MCEs after ECC setup, but do not enable
sync flood until NB setup in ramstage to allow time for any
MCEs to accumulate in the status registers. Before enabling
sync flood on MCE, determine if any MCEs were logged during
ramstage execution and display them on the serial console.
Also clear the DRAM ECC sync flood bits during DRAM training
and initial ramstage execution.
Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14192
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 |
3 files changed, 3 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2de7521d7a..0b8833124e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8024,8 +8024,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; dword &= ~(0x1 << 30); dword &= ~(0x1 << 21); + dword &= ~(0x1 << 2); Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); pDCTstat->mca_config_backed_up = 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 6031239c06..67eb2b4869 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -584,6 +584,7 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t mca_config_backed_up; uint8_t sync_flood_on_dram_err; uint8_t sync_flood_on_any_uc_err; + uint8_t sync_flood_on_uc_dram_ecc_err; /* New for LB Support */ u8 NodePresent; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd269..1077cb8f89 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } } |