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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 12:01:04 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:43:27 +0200 |
| commit | 38424987c6d19015e4572d5371a0f9f621fc46fa (patch) | |
| tree | 443fa79300e0fba4f4b66fecb04bbf7d29af1db8 /src/northbridge/amd/amdmct | |
| parent | ccf78f083cd2811c401db08b002b2b3c5273db26 (diff) | |
| download | coreboot-38424987c6d19015e4572d5371a0f9f621fc46fa.tar.xz | |
src/northbridge: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16280
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 6 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 0e59e1d2a0..0914065d2a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -644,7 +644,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, devx = pDCTstat->dev_map; if (pDCTstat->NodePresent) { - printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node); + printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node); reg = 0x40; /*Dram Base 0*/ do { val = Get_NB32(dev, reg); @@ -892,7 +892,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat, byte = mctGet_NVbits(NV_DQSTrainCTL); if (byte == 1) { /* Enable DQSRcvEn training mode */ - print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set \n"); + print_t("\t\t\tStartupDCT_D: DqsRcvEnTrain set\n"); reg = 0x78 + reg_off; val = Get_NB32(dev, reg); /* Setting this bit forces a 1T window with hard left @@ -903,7 +903,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); } mctHookBeforeDramInit(); /* generalized Hook */ - print_t("\t\t\tStartupDCT_D: DramInit \n"); + print_t("\t\t\tStartupDCT_D: DramInit\n"); mct_DramInit(pMCTstat, pDCTstat, dct); AfterDramInit_D(pDCTstat, dct); mctHookAfterDramInit(); /* generalized Hook*/ diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index f8784aff68..abc5838c54 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -511,7 +511,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, } MutualCSPassW[DQSDelay] &= tmp; - print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 \tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); + print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146\tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO_D(TestAddr); FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4fa7e66ae3..7aee892b36 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3973,7 +3973,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, val |= Node; Set_NB32(dev, 0x44 + (Node << 3), val); /* set DstNode */ - printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x \n", Node, base, limit); + printk(BIOS_DEBUG, " Node: %02x base: %02x limit: %02x\n", Node, base, limit); limit = pDCTstat->DCTSysLimit; if (limit) { NextBase = (limit & 0xFFFF0000) + 0x10000; @@ -3987,7 +3987,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, devx = pDCTstat->dev_map; if (pDCTstat->NodePresent) { - printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node); + printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x\n", Node); reg = 0x40; /*Dram Base 0*/ do { val = Get_NB32(dev, reg); |