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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-02 19:22:00 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-12 20:08:19 +0200 |
| commit | 6e8b3c11105682e58ccb0574148654adecc532f7 (patch) | |
| tree | bcd395a865e9d3f981e5ef9e99ff7b8bbfea3fe5 /src/northbridge/amd/cimx | |
| parent | 6b72787d270077969869e9b17b88a63539f172b4 (diff) | |
| download | coreboot-6e8b3c11105682e58ccb0574148654adecc532f7.tar.xz | |
src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/cimx')
| -rw-r--r-- | src/northbridge/amd/cimx/rd890/early.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index 5852aa363f..4904e5258e 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -34,7 +34,7 @@ void sr56x0_rd890_disable_pcie_bridge(void) AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); - nb_cfg->ConfigPtr = &cfg_ptr; + nb_cfg->ConfigPtr = &cfg_ptr; nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); val = (1 << 2) | (1 << 3); /*GPP1*/ val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ |