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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 17:53:38 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 17:53:38 +0000 |
| commit | 9fe4d797a37671a65053add3f7cca27397db0b9b (patch) | |
| tree | 5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/northbridge/amd/gx1/northbridge.c | |
| parent | 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff) | |
| download | coreboot-9fe4d797a37671a65053add3f7cca27397db0b9b.tar.xz | |
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx1/northbridge.c')
| -rw-r--r-- | src/northbridge/amd/gx1/northbridge.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index b652ffac08..4eb02c7ded 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -36,8 +36,8 @@ static void optimize_xbus(device_t dev) static void enable_shadow(device_t dev) { - writel(0x77777777,GX_BASE+BC_XMAP_2); - writel(0x77777777,GX_BASE+BC_XMAP_3); + write32(GX_BASE+BC_XMAP_2, 0x77777777); + write32(GX_BASE+BC_XMAP_3, 0x77777777); } static void northbridge_init(device_t dev) |