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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:05:26 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:28:48 +0200
commit15279a9696c70b82c2223264a505da9122f9aa7b (patch)
tree7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/amd/gx2
parent585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff)
downloadcoreboot-15279a9696c70b82c2223264a505da9122f9aa7b.tar.xz
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/gx2')
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index efbe51ef11..f21d717a55 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -538,7 +538,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough