changes for the lx and artecgroup mobo

Signed-off-by: Indrek Kruusa
Approved-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 23 insertions, 51 deletions

diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 3aeea646c1..f1ae87d69e 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -18,27 +18,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
    	 *   — MSR 20000019h
    	 */
    	
-   		// This is done by sdram_set_spd_registers()
-		/*WR_MSR   MC_CF07_DATA,   DIMMCONFIG, 0x05000040
-
-		;WR_MSR	MC_CF07_DATA,   DIMMCONFIG, 0x00000040		; MSR 20000018h except REF_INT bits [23:8]. REF_STAG value from DOCS*/
-		
-	/*
-	 * 0x18000100 : 0x696332A3
-	 * 
-	 * 		63 - 32 | 31                  15                0
-	 * xxxxxxx		| 0110 1001 0110 0011 0011 0010 1010 0011
-	 * 
-	 *  30:28 CAS latency
-	 * 
-	 * 010 - 2.0
-	 * 110 - 2.5
-	 *
-	 */
-
-	msr.hi = 0x18000100;
-	msr.lo = 0x696332A3;
-	wrmsr(MC_CF8F_DATA, msr);
+   	// This is done by sdram_set_spd_registers() that is called by sdram/generic_sdram.c just before this
+   	// sdram_set_spd_registers is responsible for reading ram settings from spd rom and configuring sdram conrtoller
+   	// Here follows generic sdram initialization procedure.
 
 	/* 2)  Initialize the following GLMC registers:
 	 *	— MSR 2000001Ah[15:8] = C8h
@@ -48,6 +30,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr.lo = 0x130AD101;
 	wrmsr(MC_CF1017_DATA, msr);
 
+	//ok
 	msr.hi = 0x00000000;
 	msr.lo = 0x00000001;
 	wrmsr(MC_GLD_MSR_PM, msr);
@@ -55,41 +38,37 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* 3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] = 11) */
 
 	msr.hi = 0x00000000;
-	msr.lo = 0x00001000;
+	msr.lo = 0x00000000;
 	wrmsr(MC_CFCLK_DBUG, msr);
 	
-	//print_debug("sdram_enable step 3\r\n");
+	// reset memory controller
+	msr = rdmsr(MC_CF07_DATA);
+	msr.lo |=  0x00000002;
+	wrmsr(MC_CF07_DATA, msr);
+	msr.lo &= 0xFFFFFFFD;
+	wrmsr(MC_CF07_DATA, msr);
 
 	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
 	 * why this is before EMRS and MRS ? */
 	 
 	for (i = 0; i < 19; i++) {
 		msr = rdmsr(MC_CF07_DATA);
-		msr.lo |=  (0x01 << 3);
+		msr.lo |=  0x00000008;
 		wrmsr(MC_CF07_DATA, msr);
-		msr.lo &= ~(0x01 << 3);
+		msr.lo &= 0xFFFFFFF7;
 		wrmsr(MC_CF07_DATA, msr);
 	}
 
 
 	/* 5) Initialize REF_INT (MSR 20000018h[23:8]) to set refresh interval.	*/
-	msr.lo |= 0x2B00;
+	msr.lo |= 0x3A00;
 	wrmsr(MC_CF07_DATA, msr);
 
-
-
-	/* set refresh staggering to 4 SDRAM clocks */
-	msr = rdmsr(0x20000018);
-	msr.lo &= ~(0x03 << 6);
-	msr.lo |=  (0x00 << 6);
-	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 5\r\n");
-
-
 	/* 6) Perform load-mode with MSR_BA = 01 (MSR 200000018h[29:28] = 01) 
 	 * to initialize DIMM Extended Mode register. 
 	 * Load-mode is performed by setting/clearing PROG_DRAM (MSR 200000018h[0]).
 	 */
+// eeldus et bit29 = 0, mida ta praegu ka on
 	msr.lo |=  ((0x01 << 28) | 0x01);
 	wrmsr(MC_CF07_DATA, msr);
 
@@ -100,13 +79,20 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet  */	
 	/* load Mode Register by set and clear PROG_DRAM */
+// eeldus et bit27:28=00, mida nad ka on
 	msr = rdmsr(MC_CF07_DATA);
 	msr.lo |=  ((0x01 << 27) | 0x01);
 	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~((0x01 << 27) | 0x01);
 	wrmsr(MC_CF07_DATA, msr);
-	//print_debug("sdram_enable step 7\r\n");
 
+	//Delay
+	i=inb(0x61);
+	while (i==inb(0x61));
+	i=inb(0x61);
+	while (i==inb(0x61));
+	i=inb(0x61);
+	while (i==inb(0x61));
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(MC_CF07_DATA);
@@ -114,25 +100,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	wrmsr(MC_CF07_DATA, msr);
 	msr.lo &= ~0x01;
 	wrmsr(MC_CF07_DATA, msr);
-	//print_debug("sdram_enable step 8\r\n");
 
 	/* wait 200 SDCLKs */
 	for (i = 0; i < 200; i++)
 		outb(0xaa, 0x80);
 
-	/* load RDSYNC */
-	/*msr = rdmsr(0x2000001f);
-	msr.hi = 0x000ff310;
-	msr.lo = 0x00000000;
-	wrmsr(0x2000001f, msr);*/
-
-	/* set delay control */
-	msr = rdmsr(0x4c00000f);
-	msr.hi = 0x830d415a;
-	msr.lo = 0x8ea0ad6a;
-	wrmsr(0x4c00000f, msr);
-
-
 	print_debug("DRAM controller init done.\r\n");
 
 	/* Fixes from Jordan Crouse of AMD. */