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authorAurelien Guillaume <aurelien@iwi.me>2010-08-24 12:58:17 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-08-24 12:58:17 +0000
commit6f22ecc2c920b41f5c48d96030333d1874f67c8d (patch)
treea141a64e7834e5a5f91f4c5f249801853449ffaa /src/northbridge/amd/lx
parent83628902adacc8eece332c6968ff4e910d43c5b4 (diff)
downloadcoreboot-6f22ecc2c920b41f5c48d96030333d1874f67c8d.tar.xz
* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime. Signed-off-by: Aurelien Guillaume <aurelien@iwi.me> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index d2197a7583..7240898695 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -739,7 +739,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo |= (209 << 8); /* bits[15:8] = 209 */
wrmsr(msrnum, msr);
- print_emerg("DRAM controller init done.\n");
+ banner("DRAM controller init done.\n");
post_code(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */