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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-04 16:26:44 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-06 19:04:51 +0200 |
| commit | 617536e5802a10141271d342611508d139944c69 (patch) | |
| tree | 46b5a8e94ab709d935e619088dc6d3426ed93ba6 /src/northbridge/amd/lx | |
| parent | 24850ccf9b4597a1269ac3409814219108fadf33 (diff) | |
| download | coreboot-617536e5802a10141271d342611508d139944c69.tar.xz | |
amd/gx2 + amd/lx: Fix shift overflow issue
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register
it is assigned to (rightly so):
src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of
'1077936128 << 8' requires 40 bits to represent, but 'int' only
has 32 bits [-Werror=shift-overflow=]
msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
^~
Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14617
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/lx')
| -rw-r--r-- | src/northbridge/amd/lx/northbridgeinit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index f385770bc7..08259f8cc9 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -164,7 +164,7 @@ static void SMMGL0Init(struct gliutable *gl) msr.hi = offset << 8 | gl->hi; msr.hi |= SMM_OFFSET >> 24; - msr.lo = SMM_OFFSET << 8; + msr.lo = (SMM_OFFSET & 0x00ffffff) << 8; msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above @@ -181,7 +181,7 @@ static void SMMGL1Init(struct gliutable *gl) /* I don't think this is needed */ msr.hi &= 0xffffff00; msr.hi |= (SMM_OFFSET >> 24); - msr.lo = (SMM_OFFSET << 8) & 0xFFF00000; + msr.lo = (SMM_OFFSET & 0x00fff000) << 8; msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above |