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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-10-18 17:56:42 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2007-10-18 17:56:42 +0000 |
| commit | bd7602314bd0a4fb96ddc0b055d503fa67a55303 (patch) | |
| tree | c3f15a95f1f6aa631a323970d0a01340c264d217 /src/northbridge/amd/lx | |
| parent | 69a392b5c644518ace86d43d6dd76d52f0c634af (diff) | |
| download | coreboot-bd7602314bd0a4fb96ddc0b055d503fa67a55303.tar.xz | |
Remove hardcoded wait from SPI write/erase routines and check the chip
status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/lx')
0 files changed, 0 insertions, 0 deletions