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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-27 23:45:20 +0100 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-28 00:00:30 +0100 |
| commit | fd611f9c2c8c751069c6cd1634a3e3e523ff098b (patch) | |
| tree | 3e1d3d844987a6f02d406e13f68aa37e3f55ec7e /src/northbridge/amd/lx | |
| parent | 9c29cfae8cc6214478a0a555e6901779eb19ef54 (diff) | |
| download | coreboot-fd611f9c2c8c751069c6cd1634a3e3e523ff098b.tar.xz | |
Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.
Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd/lx')
| -rw-r--r-- | src/northbridge/amd/lx/northbridge.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 3a2eb462ed..5909d1360e 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -370,9 +370,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_AMD_LXBRIDGE, }; -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -391,11 +389,9 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); |