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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-28 21:05:26 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:28:48 +0200
commit15279a9696c70b82c2223264a505da9122f9aa7b (patch)
tree7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/amd/lx
parent585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff)
downloadcoreboot-15279a9696c70b82c2223264a505da9122f9aa7b.tar.xz
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/northbridge.c4
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 0ff7917c7d..2ba4a0415d 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -46,7 +46,7 @@
#define WRITE_COMBINE (1<<4)
#define WRITE_SERIALIZE (1<<5)
-/* ram has none of this stuff */
+/* RAM has none of this stuff */
#define RAM_PROPERTIES (0)
#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
@@ -86,7 +86,7 @@ struct msr_defaults {
/* for 180a, for now, we assume VSM will configure it */
/* 180b is left at reset value,a0000-bffff is non-cacheable */
/* 180c, c0000-dffff is set to write serialize and non-cachable */
- /* oops, 180c will be set by cpu bug handling in cpubug.c */
+ /* oops, 180c will be set by CPU bug handling in cpubug.c */
//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
/* 180d is left at default, e0000-fffff is non-cached */
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 08259f8cc9..6c48fb4155 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -591,7 +591,7 @@ static void rom_shadow_settings(void)
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough