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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:47:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:47:43 +0000
commit64ed2b73451de4b655b3fdda0ff42825a165c317 (patch)
tree0faaae313a9a9edbf8b33f56fc18830ba14aa75f /src/northbridge/amd/lx
parent5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff)
downloadcoreboot-64ed2b73451de4b655b3fdda0ff42825a165c317.tar.xz
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/pll_reset.c2
-rw-r--r--src/northbridge/amd/lx/raminit.c14
2 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 45a2c9338c..08c19b48e5 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -68,7 +68,7 @@ static void pll_reset(char manualconf)
__asm__ __volatile__("hlt\n");
}
- print_debug("Done pll_reset\r\n");
+ print_debug("Done pll_reset\n");
return;
}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index d22efa61c0..15b5be6ea4 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -32,12 +32,12 @@ static void banner(const char *s)
/* This is so ugly. */
print_debug("===========================");
print_debug(s);
- print_debug("======================================\r\n");
+ print_debug("======================================\n");
}
void hcf(void)
{
- print_emerg("DIE\r\n");
+ print_emerg("DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
@@ -200,7 +200,7 @@ static void checkDDRMax(void)
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
+ print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
POST_CODE(POST_PLL_MEM_FAIL);
hcf();
}
@@ -340,7 +340,7 @@ static void setCAS(void)
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\r\n");
+ print_emerg("DIMM CAS Latencies not compatible\n");
POST_CODE(ERROR_DIFF_DIMMS);
hcf();
}
@@ -532,7 +532,7 @@ static void EnableMTest(void)
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\r\n");
+ print_info("Enabled MTest for TLA debug\n");
}
static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -576,7 +576,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\r\n");
+ print_emerg("DIMM0 NOT COMPATIBLE\n");
POST_CODE(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -649,7 +649,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\r\n");
+ print_emerg("No memory in the system\n");
POST_CODE(ERROR_NO_DIMMS);
hcf();
}