northbridge: Drop print_ implementation from non-romcc boards

Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

1 files changed, 15 insertions, 15 deletions

diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 7c95ab4bd2..d8515c645e 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -38,13 +38,13 @@ static void banner(const char *s)
 
 static void __attribute__((noreturn)) hcf(void)
 {
-	print_emerg("DIE\n");
+	printk(BIOS_EMERG, "DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also
 	 * ensures that things, in general, keep going so no debug output
 	 * is lost
 	 */
 	while (1)
-		print_emerg_char(0);
+		printk(BIOS_EMERG, "%c", 0);
 }
 
 static void auto_size_dimm(unsigned int dimm)
@@ -67,7 +67,7 @@ static void auto_size_dimm(unsigned int dimm)
 	/* EEPROM byte usage: (5) Number of DIMM Banks */
 	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
 	if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
-		print_emerg("Number of module banks not compatible\n");
+		printk(BIOS_EMERG, "Number of module banks not compatible\n");
 		post_code(ERROR_BANK_SET);
 		hcf();
 	}
@@ -78,7 +78,7 @@ static void auto_size_dimm(unsigned int dimm)
 	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
 	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
 	if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
-		print_emerg("Number of device banks not compatible\n");
+		printk(BIOS_EMERG, "Number of device banks not compatible\n");
 		post_code(ERROR_BANK_SET);
 		hcf();
 	}
@@ -94,7 +94,7 @@ static void auto_size_dimm(unsigned int dimm)
 	 */
 	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
 	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
-		print_emerg("Assymetirc DIMM not compatible\n");
+		printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
@@ -111,7 +111,7 @@ static void auto_size_dimm(unsigned int dimm)
 	dimm_size = __builtin_ctz(dimm_size);
 	banner("TEST DIMM SIZE>8");
 	if (dimm_size > 8) {	/* 8 is 1GB only support 1GB per DIMM */
-		print_emerg("Only support up to 1 GB per DIMM\n");
+		printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
 		post_code(ERROR_DENSITY_DIMM);
 		hcf();
 	}
@@ -144,7 +144,7 @@ static void auto_size_dimm(unsigned int dimm)
 	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
 	banner("MAXCOLADDR");
 	if (spd_byte > MAX_COL_ADDR) {
-		print_emerg("DIMM page size not compatible\n");
+		printk(BIOS_EMERG, "DIMM page size not compatible\n");
 		post_code(ERROR_SET_PAGE);
 		hcf();
 	}
@@ -186,7 +186,7 @@ static void checkDDRMax(void)
 
 	/* I don't think you need this check.
 	   if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
-	   print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+	   printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
 	   post_code(POST_PLL_MEM_FAIL);
 	   hcf();
 	   } */
@@ -201,7 +201,7 @@ static void checkDDRMax(void)
 
 	/* current speed > max speed? */
 	if (GeodeLinkSpeed() > speed) {
-		print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
 		post_code(POST_PLL_MEM_FAIL);
 		hcf();
 	}
@@ -319,7 +319,7 @@ static void setCAS(void)
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz(casmap0)];
 	} else {
-		print_emerg("DIMM CAS Latencies not compatible\n");
+		printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
 		post_code(ERROR_DIFF_DIMMS);
 		hcf();
 	}
@@ -513,7 +513,7 @@ static void EnableMTest(void)
 	msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
 	wrmsr(MC_CFCLK_DBUG, msr);
 
-	print_info("Enabled MTest for TLA debug\n");
+	printk(BIOS_INFO, "Enabled MTest for TLA debug\n");
 }
 #endif
 
@@ -558,14 +558,14 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	banner("Check DIMM 0");
 	/* Check DIMM is not Register and not Buffered DIMMs. */
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		print_emerg("DIMM0 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
 	banner("Check DIMM 1");
 	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		print_emerg("DIMM1 NOT COMPATIBLE\n");
+		printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
 		post_code(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
@@ -633,7 +633,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr = rdmsr(MC_CF07_DATA);
 	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
 			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
-		print_emerg("No memory in the system\n");
+		printk(BIOS_EMERG, "No memory in the system\n");
 		post_code(ERROR_NO_DIMMS);
 		hcf();
 	}
@@ -775,6 +775,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		msr.lo |= 1;
 		wrmsr(msrnum, msr);
 	}
-	print_info("RAM DLL lock\n");
+	printk(BIOS_INFO, "RAM DLL lock\n");
 
 }