diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-12-30 19:21:08 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-12-30 19:21:08 +0000 |
| commit | 8cf54c9f236afef6b74b6510983bd25e8536055a (patch) | |
| tree | eb42ed594d392e4b44220b78de30f90848d312c5 /src/northbridge/amd/lx | |
| parent | f1939bb29b15cb68e90c68ceda86d8d9ad20e746 (diff) | |
| download | coreboot-8cf54c9f236afef6b74b6510983bd25e8536055a.tar.xz | |
Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/lx')
| -rw-r--r-- | src/northbridge/amd/lx/pll_reset.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 1f8e499825..3077b61c9c 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -59,9 +59,8 @@ static void pll_reset(char manualconf) wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); /* You should never get here..... The chip has reset. */ - printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n"); post_code(POST_PLL_RESET_FAIL); - __asm__ __volatile__("hlt\n"); + die("CONFIGURING PLL FAILURE\n"); } printk(BIOS_DEBUG, "PLL configured.\n"); |