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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-11-24 14:16:34 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-04 12:23:50 +0000
commit73a544d4533fa8305f1c0a809137b5e2151ea17e (patch)
treee7d0b63098c2d021b579599a9ce419d3ced9db52 /src/northbridge/amd/pi
parentc08fdf3decc6a61a9020a7df484d92473f7223e9 (diff)
downloadcoreboot-73a544d4533fa8305f1c0a809137b5e2151ea17e.tar.xz
soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function
According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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