diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-19 19:57:01 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-05-27 13:54:47 +0200 |
| commit | 70d92b9465b1edf646b25b89f1442f7107b5f1f6 (patch) | |
| tree | 8d0a39990358f3fd92b00f0e790b7667ca90fd1c /src/northbridge/amd/pi | |
| parent | ef8bb9136e9371753e50cb15b334c9d0f5c70930 (diff) | |
| download | coreboot-70d92b9465b1edf646b25b89f1442f7107b5f1f6.tar.xz | |
CBMEM: Clarify CBMEM_TOP_BACKUP function usage
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/northbridge/amd/pi')
| -rw-r--r-- | src/northbridge/amd/pi/agesawrapper.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/ramtop.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index ec1d0acf9f..d4b9984f81 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -153,9 +153,9 @@ AGESA_STATUS agesawrapper_amdinitpost(void) * UMA may or may not be cacheable, so Sub4GCacheTop could be * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ if (PostParams->MemConfig.UmaBase) - backup_top_of_ram(PostParams->MemConfig.UmaBase << 16); + backup_top_of_low_cacheable(PostParams->MemConfig.UmaBase << 16); else - backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop); + backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop); printk( BIOS_SPEW, diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c index 2b501dcf05..8fa81c715a 100644 --- a/src/northbridge/amd/pi/ramtop.c +++ b/src/northbridge/amd/pi/ramtop.c @@ -19,13 +19,13 @@ #define CBMEM_TOP_SCRATCHPAD 0x78 -void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_low_cacheable(uintptr_t ramtop) { uint16_t top_cache = ramtop >> 16; pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); } -unsigned long get_top_of_ram(void) +uintptr_t restore_top_of_low_cacheable(void) { uint16_t top_cache; top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); |