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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 00:24:21 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 00:24:21 +0000
commit1f93fea160fff042f7d5467c56eaf2fc0286995f (patch)
tree19b70c9576ea9869caed82def385177d4a08488e /src/northbridge/amd
parent0e5d3e16b494aafa3c08a28a0484ee0845d84512 (diff)
downloadcoreboot-1f93fea160fff042f7d5467c56eaf2fc0286995f.tar.xz
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. BKDG says nbSynPtrAdj may also be 6 sometimes. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdht/AsPsDefs.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 2ef46ffe9e..3907208290 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -181,6 +181,8 @@
#define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/
#define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */
#define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */
+#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */
+#define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */
#define PRCT_INFO 0x1fc /* Product Info Register */
#define UNI_NB_FID_BIT 2 /* UniNbFid bit position */
@@ -224,6 +226,10 @@
/* F4x1F4 Northbridge P-state spec register */
#define NB_PS_SPEC_REG 0x1f4 /* Nb PS spec reg */
+/* F3x1F0 Product Information Register */
+#define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */
+
+
#define NM_PS_REG 5 /* number of P-state MSR registers */
/* sFidVidInit.outFlags defines */