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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 09:56:08 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-24 13:33:57 +0000 |
| commit | 21fa51475d86e5c68b5dd46233fb7889516def78 (patch) | |
| tree | 221097b6ab0fe159f1b45d467bdf987451de3fd5 /src/northbridge/amd | |
| parent | bb748c5f92325b3342aed0286c05a4f8e385fd29 (diff) | |
| download | coreboot-21fa51475d86e5c68b5dd46233fb7889516def78.tar.xz | |
AMD geode/lx: Remove generic_sdram.c include
The file under lib/ will be removed with K8 and
Geode LX is the only other platform using it.
Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/lx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/generic_sdram.c | 29 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc index 19d9e44db6..190c0598e4 100644 --- a/src/northbridge/amd/lx/Makefile.inc +++ b/src/northbridge/amd/lx/Makefile.inc @@ -5,5 +5,6 @@ ramstage-y += northbridgeinit.c ramstage-y += grphinit.c romstage-y += raminit.c +romstage-y += generic_sdram.c endif diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c new file mode 100644 index 0000000000..21239c6c17 --- /dev/null +++ b/src/northbridge/amd/lx/generic_sdram.c @@ -0,0 +1,29 @@ +#include <console/console.h> +#include <northbridge/amd/lx/raminit.h> + +/* Setup SDRAM */ +void sdram_initialize(int controllers, const struct mem_controller *ctrl) +{ + int i; + /* Set the registers we can set once to reasonable values */ + for (i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram1.%02x\n", i); + sdram_set_registers(ctrl + i); + } + + /* Now setup those things we can auto detect */ + for (i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram2.%02x\n", i); + sdram_set_spd_registers(ctrl + i); + } + + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for us while on others + * we need to it by hand. + */ + printk(BIOS_DEBUG, "Ram3\n"); + + sdram_enable(controllers, ctrl); + + printk(BIOS_DEBUG, "Ram4\n"); +} |