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authorStefan Reinauer <reinauer@chromium.org>2015-07-30 16:25:33 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-30 18:20:11 +0100
commit6a2df9a5e88fc5176994944b66227224d4e2a842 (patch)
tree5fef4d408ca0859d1a14889e9a250b3e187defb4 /src/northbridge/amd
parent59d0e040c89b5eea5f2febfa73de57d45a9ae535 (diff)
downloadcoreboot-6a2df9a5e88fc5176994944b66227224d4e2a842.tar.xz
RD890: 64bit fixes
Change-Id: I326c070398c72a877054969d3a03e6e427edc304 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11086 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/cimx/rd890/late.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index bc51543cbc..3bdce272ca 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -86,7 +86,8 @@ static void rd890_enable(device_t dev)
/* CIMX configuration defualt initialize */
rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
if (gConfig.StandardHeader.CalloutPtr != NULL) {
- gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr);
+ gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig,
+ (uintptr_t)dev, (VOID*)NbConfigPtr);
}
/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
* After this call EP are fully operational on particular NB
@@ -122,7 +123,7 @@ static void ioapic_init(struct device *dev)
void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1);
- ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
+ ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1);
}