src/northbridge: Improve code formatting

Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

17 files changed, 220 insertions, 227 deletions

diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 1c8f904621..53ddc0e5b1 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -41,8 +41,8 @@ extern uint32_t agesawrapper_amdinitmid(void);
 
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
 typedef struct dram_base_mask {
-        u32 base; //[47:27] at [28:8]
-        u32 mask; //[47:27] at [28:8] and enable at bit 0
+	u32 base; //[47:27] at [28:8]
+	u32 mask; //[47:27] at [28:8] and enable at bit 0
 } dram_base_mask_t;
 
 
@@ -162,7 +162,6 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 				u32 io_min, u32 io_max)
 {
-
 	u32 i;
 	u32 tempreg;
 
@@ -189,7 +188,6 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 
 static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
 {
-
 	u32 i;
 	u32 tempreg;
 
@@ -218,9 +216,9 @@ static device_t get_node_pci(u32 nodeid, u32 fn)
 
 static unsigned int read_nb_cfg_54(void)
 {
-        msr_t msr;
-        msr = rdmsr(NB_CFG_MSR);
-        return (( msr.hi >> (54-32)) & 1);
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	return (( msr.hi >> (54-32)) & 1);
 }
 
 static void get_fx_devs(void)
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index df6b3e4f93..15269727d8 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -269,47 +269,47 @@ struct hw_mem_hole_info {
 
 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 {
-        struct hw_mem_hole_info mem_hole;
-
-        mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
-        mem_hole.node_id = -1;
-
-        struct dram_base_mask_t d;
-        u32 hole;
-        d = get_dram_base_mask(0);
-        if (d.mask & 1) {
-            hole = pci_read_config32(__f1_dev[0], 0xf0);
-            if (hole & 1) { // we find the hole
-                mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
-                mem_hole.node_id = 0; // record the node No with hole
-            }
-        }
+	struct hw_mem_hole_info mem_hole;
+
+	mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+	mem_hole.node_id = -1;
+
+	struct dram_base_mask_t d;
+	u32 hole;
+	d = get_dram_base_mask(0);
+	if (d.mask & 1) {
+		hole = pci_read_config32(__f1_dev[0], 0xf0);
+		if (hole & 1) { // we find the hole
+			mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+			mem_hole.node_id = 0; // record the node No with hole
+		}
+	}
 
 #if 0
 	/* We need to double check if there is special set on base reg and limit reg
 	 * are not continuous instead of hole, it will find out its hole_startk.
 	 */
-        if (mem_hole.node_id==-1) {
-            resource_t limitk_pri = 0;
-            struct dram_base_mask_t d;
-            resource_t base_k, limit_k;
-            d = get_dram_base_mask(0);
-            if (d.base & 1) {
-                base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
-                if (base_k <= 4 *1024 * 1024) {
-                    if (limitk_pri != base_k) { // we find the hole
-                        mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
-                        mem_hole.node_id = 0;
-                    }
-                }
-
-                limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
-                limitk_pri = limit_k;
-            }
-        }
+	if (mem_hole.node_id==-1) {
+		resource_t limitk_pri = 0;
+		struct dram_base_mask_t d;
+		resource_t base_k, limit_k;
+		d = get_dram_base_mask(0);
+		if (d.base & 1) {
+			base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+			if (base_k <= 4 *1024 * 1024) {
+				if (limitk_pri != base_k) { // we find the hole
+					mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
+					mem_hole.node_id = 0;
+				}
+			}
+
+		limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
+		limitk_pri = limit_k;
+		}
+	}
 #endif
 
-        return mem_hole;
+	return mem_hole;
 }
 #endif
 
@@ -471,44 +471,44 @@ static void setup_uma_memory(void)
 
 static void domain_read_resources(device_t dev)
 {
-    unsigned reg;
-
-    printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-    /* Find the already assigned resource pairs */
-    get_fx_devs();
-    for (reg = 0x80; reg <= 0xc0; reg+= 0x08) {
-        u32 base, limit;
-        base  = f1_read_config32(reg);
-        limit = f1_read_config32(reg + 0x04);
-        /* Is this register allocated? */
-        if ((base & 3) != 0) {
-            unsigned nodeid, reg_link;
-            device_t reg_dev;
-            if (reg<0xc0) { // mmio
-                nodeid = (limit & 0xf) + (base&0x30);
-            } else { // io
-                nodeid =  (limit & 0xf) + ((base>>4)&0x30);
-            }
-            reg_link = (limit >> 4) & 7;
-            reg_dev = __f0_dev[nodeid];
-            if (reg_dev) {
-                /* Reserve the resource  */
-                struct resource *res;
-                res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
-                if (res) {
-                    res->flags = 1;
-                }
-            }
-        }
-    }
-    /* FIXME: do we need to check extend conf space?
-       I don't believe that much preset value */
-
-    struct resource *resource;
-	/* Initialize the system-wide I/O space constraints. */
+	unsigned reg;
+
+	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
+
+	/* Find the already assigned resource pairs */
+	get_fx_devs();
+	for (reg = 0x80; reg <= 0xc0; reg+= 0x08) {
+		u32 base, limit;
+		base  = f1_read_config32(reg);
+		limit = f1_read_config32(reg + 0x04);
+		/* Is this register allocated? */
+		if ((base & 3) != 0) {
+			unsigned nodeid, reg_link;
+			device_t reg_dev;
+			if (reg<0xc0) { // mmio
+				nodeid = (limit & 0xf) + (base&0x30);
+			} else { // io
+				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
+			}
+			reg_link = (limit >> 4) & 7;
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
+				/* Reserve the resource  */
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+				if (res) {
+					res->flags = 1;
+				}
+			}
+		}
+	}
+	/* FIXME: do we need to check extend conf space?
+	I don't believe that much preset value */
+
+	struct resource *resource;
+		/* Initialize the system-wide I/O space constraints. */
 	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-    resource->base  = 0x1000;
+	resource->base  = 0x1000;
 	resource->limit = 0xffffUL;
 	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED;
@@ -520,40 +520,40 @@ static void domain_read_resources(device_t dev)
 	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED;
 
-    printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
+	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
 }
 
 
 static void domain_set_resources(device_t dev)
 {
-    printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-    printk(BIOS_DEBUG, "  amsr - incoming dev = %p\n", dev);
-
-    unsigned long mmio_basek;
-    u32 pci_tolm;
-    u64 ramtop = 0;
-    int idx;
-    struct bus *link;
+	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
+	printk(BIOS_DEBUG, "  amsr - incoming dev = %p\n", dev);
+
+	unsigned long mmio_basek;
+	u32 pci_tolm;
+	u64 ramtop = 0;
+	int idx;
+	struct bus *link;
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
-    struct hw_mem_hole_info mem_hole;
-    u32 reset_memhole = 1;
+	struct hw_mem_hole_info mem_hole;
+	u32 reset_memhole = 1;
 #endif
 
-    pci_tolm = 0xffffffffUL;
-    for (link = dev->link_list; link; link = link->next) {
-        pci_tolm = my_find_pci_tolm(link, pci_tolm);
-    }
+	pci_tolm = 0xffffffffUL;
+	for (link = dev->link_list; link; link = link->next) {
+		pci_tolm = my_find_pci_tolm(link, pci_tolm);
+	}
 
-    // FIXME handle interleaved nodes. If you fix this here, please fix
-    // amdk8, too.
-    mmio_basek = pci_tolm >> 10;
-    /* Round mmio_basek to something the processor can support */
-    mmio_basek &= ~((1 << 6) -1);
+	// FIXME handle interleaved nodes. If you fix this here, please fix
+	// amdk8, too.
+	mmio_basek = pci_tolm >> 10;
+	/* Round mmio_basek to something the processor can support */
+	mmio_basek &= ~((1 << 6) -1);
 
-    // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
-    // MMIO hole. If you fix this here, please fix amdk8, too.
-    /* Round the mmio hole to 64M */
-    mmio_basek &= ~((64*1024) - 1);
+	// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+	// MMIO hole. If you fix this here, please fix amdk8, too.
+	/* Round the mmio hole to 64M */
+	mmio_basek &= ~((64*1024) - 1);
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 /* if the hw mem hole is already set in raminit stage, here we will compare
@@ -562,77 +562,76 @@ static void domain_set_resources(device_t dev)
  * otherwise We reset the hole to the mmio_basek
  */
 
-    mem_hole = get_hw_mem_hole_info();
+	mem_hole = get_hw_mem_hole_info();
 
-    // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
-    if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
-        mmio_basek = mem_hole.hole_startk;
-        reset_memhole = 0;
-    }
+	// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+	if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
+		mmio_basek = mem_hole.hole_startk;
+		reset_memhole = 0;
+	}
 #endif
 
-    idx = 0x10;
+	idx = 0x10;
 
-    struct dram_base_mask_t d;
-    resource_t basek, limitk, sizek; // 4 1T
+	struct dram_base_mask_t d;
+	resource_t basek, limitk, sizek; // 4 1T
 
-    d = get_dram_base_mask(0);
+	d = get_dram_base_mask(0);
 
-    if (d.mask & 1) {
-        basek = ((resource_t)(d.base)) << 8;
-        limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
-printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
+	if (d.mask & 1) {
+		basek = ((resource_t)(d.base)) << 8;
+		limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
+		printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
 
-        /* Convert these values to multiples of 1K for ease of math. */
-        basek >>= 10;
-        limitk >>= 10;
-        sizek = limitk - basek + 1;
+		/* Convert these values to multiples of 1K for ease of math. */
+		basek >>= 10;
+		limitk >>= 10;
+		sizek = limitk - basek + 1;
 
-printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
+		printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
 
-        /* see if we need a hole from 0xa0000 to 0xbffff */
-        if ((basek < 640) && (sizek > 768)) {
-printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
-            ram_resource(dev, (idx | 0), basek, 640 - basek);
-            idx += 0x10;
-            basek = 768;
-            sizek = limitk - 768;
-        }
+		/* see if we need a hole from 0xa0000 to 0xbffff */
+		if ((basek < 640) && (sizek > 768)) {
+			printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
+			ram_resource(dev, (idx | 0), basek, 640 - basek);
+			idx += 0x10;
+			basek = 768;
+			sizek = limitk - 768;
+		}
 
 		printk(BIOS_DEBUG,
 			"adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 			 mmio_basek, basek, limitk);
 
-        /* split the region to accommodate pci memory space */
-        if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
-            if (basek <= mmio_basek) {
-                unsigned pre_sizek;
-                pre_sizek = mmio_basek - basek;
-                if (pre_sizek>0) {
-                    ram_resource(dev, idx, basek, pre_sizek);
-                    idx += 0x10;
-                    sizek -= pre_sizek;
-                    if (!ramtop)
-                            ramtop = mmio_basek * 1024;
-                }
-                basek = mmio_basek;
-            }
-            if ((basek + sizek) <= 4*1024*1024) {
-                sizek = 0;
-            }
-            else {
-                basek = 4*1024*1024;
-                sizek -= (4*1024*1024 - mmio_basek);
-            }
-        }
-
-        ram_resource(dev, (idx | 0), basek, sizek);
-        idx += 0x10;
-        printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
-                 0, mmio_basek, basek, limitk);
-        if (!ramtop)
-                 ramtop = limitk * 1024;
-    }
+		/* split the region to accommodate pci memory space */
+		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+			if (basek <= mmio_basek) {
+				unsigned pre_sizek;
+				pre_sizek = mmio_basek - basek;
+				if (pre_sizek>0) {
+					ram_resource(dev, idx, basek, pre_sizek);
+					idx += 0x10;
+					sizek -= pre_sizek;
+					if (!ramtop)
+						ramtop = mmio_basek * 1024;
+				}
+				basek = mmio_basek;
+			}
+			if ((basek + sizek) <= 4*1024*1024) {
+				sizek = 0;
+			} else {
+				basek = 4*1024*1024;
+				sizek -= (4*1024*1024 - mmio_basek);
+			}
+		}
+
+		ram_resource(dev, (idx | 0), basek, sizek);
+		idx += 0x10;
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+		   0, mmio_basek, basek, limitk);
+		if (!ramtop)
+			ramtop = limitk * 1024;
+	}
 	printk(BIOS_DEBUG, "  adsr - mmio_basek = %lx.\n", mmio_basek);
 
 #if CONFIG_GFXUMA
@@ -642,13 +641,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
 	set_top_of_ram(ramtop);
 #endif
 
-    for (link = dev->link_list; link; link = link->next) {
-        if (link->children) {
-            assign_resources(link);
-        }
-    }
-printk(BIOS_DEBUG, "  adsr - leaving this lovely routine.\n");
-    printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
+	for (link = dev->link_list; link; link = link->next) {
+		if (link->children)
+			assign_resources(link);
+	}
+	printk(BIOS_DEBUG, "  adsr - leaving this lovely routine.\n");
+	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
 }
 
 
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index f347b63409..0c14bdd2d5 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -1080,9 +1080,9 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 
-                        u8 plat_num_io_apics = 3; /* FIXME */
+			u8 plat_num_io_apics = 3; /* FIXME */
 
 			if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
 				lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index ccb256b6b7..d1560b7378 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -1070,9 +1070,9 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 
-                        u8 plat_num_io_apics = 3; /* FIXME */
+			u8 plat_num_io_apics = 3; /* FIXME */
 
 			if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
 				lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 63ca2af5b1..7b57cc31e5 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -1069,9 +1069,9 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 
-                        u8 plat_num_io_apics = 3; /* FIXME */
+			u8 plat_num_io_apics = 3; /* FIXME */
 
 			if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
 				lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index c0769e725d..28302efe7b 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -1086,9 +1086,9 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 
-                        u8 plat_num_io_apics = 3; /* FIXME */
+			u8 plat_num_io_apics = 3; /* FIXME */
 
 			if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
 				lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h
index 60dc00fe2b..daf429d91a 100644
--- a/src/northbridge/amd/amdfam10/chip.h
+++ b/src/northbridge/amd/amdfam10/chip.h
@@ -19,7 +19,7 @@
 #include <stdint.h>
 
 struct northbridge_amd_amdfam10_config {
-        uint64_t maximum_memory_capacity;
+	uint64_t maximum_memory_capacity;
 };
 
 #endif /* _AMD_FAM10_CHIP_H_ */
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index e2d158f49c..64092ffc64 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -249,38 +249,38 @@ void ErrorStop(u32 value)
 ;
 ; For use with SimNow the unrotated error code is also written to port 84h
 ErrorStop   PROC FAR PASCAL PUBLIC Value:DWORD
-        pushad
-        mov     eax, Value
-        mov     bx, 0DEADh
-        out     84h, eax
+	pushad
+	mov     eax, Value
+	mov     bx, 0DEADh
+	out     84h, eax
 
 ErrorStopTop:
-        out     80h, eax
+	out     80h, eax
 
-        mov     cx, 4           ; Rotate the display by one nibble
+	mov     cx, 4           ; Rotate the display by one nibble
 @@:
-        bt      bx, 15
-        rcl     eax, 1
-        rcl     bx, 1
-        loop    @B
+	bt      bx, 15
+	rcl     eax, 1
+	rcl     bx, 1
+	loop    @B
 
 
-        push    eax             ; Delay a few hundred milliseconds
-        push    ebx
-        mov     ecx, 10h        ; TSC
-        db      00Fh, 032h      ; RDMSR
-        mov     ebx, eax
+	push    eax             ; Delay a few hundred milliseconds
+	push    ebx
+	mov     ecx, 10h        ; TSC
+	db      00Fh, 032h      ; RDMSR
+	mov     ebx, eax
 @@:
-        db      00Fh, 032h      ; RDMSR
-        sub     eax, ebx
-        cmp     eax, 500000000
-        jb      @B
-        pop     ebx
-        pop     eax
+	db      00Fh, 032h      ; RDMSR
+	sub     eax, ebx
+	cmp     eax, 500000000
+	jb      @B
+	pop     ebx
+	pop     eax
 
-        jmp     ErrorStopTop
+	jmp     ErrorStopTop
 
-        popad
-        ret
+	popad
+	ret
 ErrorStop   ENDP
 */
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index f31fcd228d..0dfc6abf64 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -29,9 +29,9 @@
 /* Single CPU system? */
 #if (CONFIG_MAX_PHYSICAL_CPUS == 1)
 	/* FIXME
-         * This #define is used by other #included .c files
+	 * This #define is used by other #included .c files
 	 * When set, multiprocessor support is completely disabled
-         */
+	 */
 	#define HT_BUILD_NC_ONLY 1
 #endif
 
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index 05117f799d..2cde1663eb 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -6,9 +6,9 @@
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 
-        #include "f.h"
+	#include "f.h"
 #else
-        #include "pre_f.h"
+	#include "pre_f.h"
 #endif
 
 #ifdef __PRE_RAM__
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 0c37366845..08d8d43ff3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2398,10 +2398,10 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec
 
 	tsc_msr = rdmsr(0x00000010);
 	start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
-        do {
+	do {
 		tsc_msr = rdmsr(0x00000010);
 		current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
-        } while ((current_timestamp - start_timestamp) < cycle_count);
+	} while ((current_timestamp - start_timestamp) < cycle_count);
 }
 
 static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 324e35e980..802417971f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -930,7 +930,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
 			 */
 			for (lane = 0; lane < 8; lane++) {
 				if (trained[lane]) {
-                        		pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
+					pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
 				} else {
 					printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel);
 
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 0ba2d33a7f..143468a7e4 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -476,34 +476,31 @@ static void mctHookAfterDramInit(void)
 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 static void vErratum372(struct DCTStatStruc *pDCTstat)
 {
-        msr_t msr = rdmsr(NB_CFG_MSR);
+	msr_t msr = rdmsr(NB_CFG_MSR);
 
 	int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32)));
 
-        // is this the right way to check for NB pstate 1 or DDR3-1333 ?
-        if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
-            &&(!pDCTstat->GangedMode)) {
-           	/* DisableCf8ExtCfg */
-        	msr.hi &= ~(3 << (51 - 32));
-        	wrmsr(NB_CFG_MSR, msr);
-        }
+	// is this the right way to check for NB pstate 1 or DDR3-1333 ?
+	if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+	    &&(!pDCTstat->GangedMode)) {
+		/* DisableCf8ExtCfg */
+		msr.hi &= ~(3 << (51 - 32));
+		wrmsr(NB_CFG_MSR, msr);
+	}
 }
 
 static void vErratum414(struct DCTStatStruc *pDCTstat)
 {
-     int dct=0;
-    for (; dct < 2 ; dct++)
-    {
-        int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
+	int dct=0;
+	for (; dct < 2 ; dct++) {
+		int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
 		int powerDown =  dRAMConfigHi & (1 << PowerDownEn );
 		int ddr3 = dRAMConfigHi & (1 << Ddr3Mode );
-        int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
+		int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
 		int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel);
-	if (powerDown && ddr3 && pchgPDModeSel )
-	{
-	  Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
+		if (powerDown && ddr3 && pchgPDModeSel )
+			Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
 	}
-    }
 }
 #endif
 
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c
index 5852aa363f..4904e5258e 100644
--- a/src/northbridge/amd/cimx/rd890/early.c
+++ b/src/northbridge/amd/cimx/rd890/early.c
@@ -34,7 +34,7 @@ void sr56x0_rd890_disable_pcie_bridge(void)
 	AMD_NB_CONFIG_BLOCK	*cfg_ptr = &cfg_block;
 	AMD_NB_CONFIG		*nb_cfg  = &(cfg_block.Northbridges[0]);
 
-        nb_cfg->ConfigPtr = &cfg_ptr;
+	nb_cfg->ConfigPtr = &cfg_ptr;
 	nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
 	val = (1 << 2) | (1 << 3); /*GPP1*/
 	val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index c55cefb359..0f9e5f5366 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 			if ((node_nums * core_max) + ioapic_count >= 0x10) {
 				lapicid_start = (ioapic_count - 1) / core_max;
 				lapicid_start = (lapicid_start + 1) * core_max;
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 1caecf9850..efee0a4f05 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 			if ((node_nums * core_max) + ioapic_count >= 0x10) {
 				lapicid_start = (ioapic_count - 1) / core_max;
 				lapicid_start = (lapicid_start + 1) * core_max;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 6f7f993046..6d5418a532 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -1108,7 +1108,7 @@ static void cpu_bus_scan(device_t dev)
 			 *
 			 * This is needed because many IO-APIC devices only have 4 bits
 			 * for their APIC id and therefore must reside at 0..15
-                         */
+			 */
 			if ((node_nums * core_max) + ioapic_count >= 0x10) {
 				lapicid_start = (ioapic_count - 1) / core_max;
 				lapicid_start = (lapicid_start + 1) * core_max;